CHRONTEL
CH7003B
8
201-0000-023 Rev.4.1, 8/2/99
Digital Video Interface (continued)
When IDF = 1, (YCrCb 16-bit mode), H and V sync signals can be embedded into the data stream. In this mode, the
embedded sync will be similar to the CCIR656 convention (not identical, since that convention is for 8-bit data
streams), and the first byte of the ‘video timing reference code’ will be assumed to occur when a Cb sample would
occur – if the video stream was continuous. This is delineated in
Table 4 below.
In this mode, the S[7..0] byte contains the following data:
S[6]
=
F
=
1 during field 2, 0 during field 1
S[5]
=
V
=
1 during field blanking, 0 elsewhere
S[4]
=
H
=
1 during EAV (the synchronization reference at the end of active video)
0 during SAV (the synchronization reference at the start of active video)
Bits S[7] and S[3..0] are ignored.
Multiplexed Mode
Each rising edge (or each rising and falling edge) of the XCLK signal will latch data from the graphics chip. The
multiplexed input data formats are shown in Figure 5 and 6.
The Pixel Data bus represents an 8-, 12-, or 16-bit
multiplexed data stream, which contains either RGB or YCrCb formatted data. In IDF settings of 2, 4, 5, 7, 8, and 9,
the input data rate is 2X PCLK, and each pair of Pn values (e.g., P0a and P0b) will contain a complete pixel,
encoded as shown in the tables below. When IDF = 6, the input data rate is 3X PCLK, and each triplet of Pn values
(e.g., P0a, P0b and P0c) will contain a complete pixel, encoded as shown in the tables below. When the input is
YCrCb, the color-difference data will be transmitted at half the data rate of the luminance data, with the sequence
being set as Cb, Y, Cr, Y where Cb0,Y0,Cr0 refers to co-sited luminance and color-difference samples — and the
following Y1 byte refers to the next luminance sample, per CCIR656 standards. However, the clock frequency is
dependent upon the current mode (not 27MHz, as specified in CCIR656.)
Table 4. YCrCb Non-multiplexed Mode with Embedded Syncs
IDF#
Format
1
YCrCb 16-bit
Pixel#
P0
P1
P2
P3
P4
P5
P6
P7
Bus Data
D[15]
0
S[7]
Y0[7]
Y1[7]
Y2[7]
Y3[7]
Y4[7]
Y5[7]
D[14]
0
S[6]
Y0[6]
Y1[6]
Y2[6]
Y3[6]
Y4[6]
Y5[6]
D[13]
0
S[5]
Y0[5]
Y1[5]
Y2[5]
Y3[5]
Y4[5]
Y5[5]
D[12]
0
S[4]
Y0[4]
Y1[4]
Y2[4]
Y3[4]
Y4[4]
Y5[4]
D[11]
0
S[3]
Y0[3]
Y1[3]
Y2[3]
Y3[3]
Y4[3]
Y5[3]
D[10]
0
S[2]
Y0[2]
Y1[2]
Y2[2]
Y3[2]
Y4[2]
Y5[2]
D[9]
0
S[1]
Y0[1]
Y1[1]
Y2[1]
Y3[1]
Y4[1]
Y5[1]
D[8]
0
S[0]
Y0[0]
Y1[0]
Y2[0]
Y3[0]
Y4[0]
Y5[0]
D[7]
1
0
Cb0[7]
Cr0[7]
Cb2[7]
Cr2[7]
Cb4[7]
Cr4[7]
D[6]
1
0
Cb0[6]
Cr0[6]
Cb2[6]
Cr2[6]
Cb4[6]
Cr4[6]
D[5]
1
0
Cb0[5]
Cr0[5]
Cb2[5]
Cr2[5]
Cb4[5]
Cr4[5]
D[4]
1
0
Cb0[4]
Cr0[4]
Cb2[4]
Cr2[4]
Cb4[4]
Cr4[4]
D[3]
1
0
Cb0[3]
Cr0[3]
Cb2[3]
Cr2[3]
Cb4[3]
Cr4[3]
D[2]
1
0
Cb0[2]
Cr0[2]
Cb2[2]
Cr2[2]
Cb4[2]
Cr4[2]
D[1]
1
0
Cb0[1]
Cr0[1]
Cb2[1]
Cr2[1]
Cb4[1]
Cr4[1]
D[0]
1
0
Cb0[0]
Cr0[0]
Cb2[0]
Cr2[0]
Cb4[0]
Cr4[0]
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