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X5325V14I Datasheet(PDF) 8 Page - Intersil Corporation |
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X5325V14I Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 21 page  8 FN8131.1 October 27, 2005 The Write Enable Latch (WEL) bit indicates the sta- tus of the write enable latch. When WEL = 1, the latch is set HIGH and when WEL = 0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction. The block lock bits, BL0 and BL1, set the level of block lock protection. These nonvolatile bits are programmed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the EEPROM array. Any portion of the array that is block lock protected can be read but not written. It will remain protected until the BL bits are altered to disable block lock protection of that portion of memory. The watchdog timer bits, WD0 and WD1, select the watchdog time out period. These nonvolatile bits are programmed with the WRSR instruction. The FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The flag bit is automatically reset upon power-up. This flag can be used by the system to determine whether a reset occurs as a result of a watchdog time out or power failure. Notes: 1. The Watch Dog Timer is shipped disabled. (WD1 = 1, WD0 = 1) 2. The factory default for Memory Block Protection is ‘None’. (BL1 = 0, BL0 = 0) Figure 5. Read EEPROM Array Sequence Status Register Bits Array Addresses Protected BL1 BL0 X5323/X5325 0 0 None (factory default) 0 1 $0C00-$0FFF 1 0 $0800-$0FFF 1 1 $0000-$0FFF Status Register Bits Watchdog Time Out (Typical) WD1 WD0 0 0 1.4 seconds 0 1 600 milliseconds 1 0 200 milliseconds 1 1 disabled (factory default) 0 1 2 3 4 5 6 7 8 9 10 20 21 22 23 24 25 26 27 28 29 30 7 6 543 21 0 Data Out CS SCK SI SO MSB High Impedance Instruction 16 Bit Address 15 14 13 3 2 1 0 X5323, X5325 |
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