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MC33470 Datasheet(PDF) 10 Page - ON Semiconductor |
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MC33470 Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 16 page MC33470 10 MOTOROLA ANALOG IC DEVICE DATA In this design, choose two parallel MMSF3300 MOSFETs for both the main switch and the synchronous rectifier to maximize efficiency. 2. D ≈ VO/Vin = 2.8/5.0 = 0.56 3. Inductor selection In order to maintain continuous mode operation at 10% of full load current, the minimum value of the inductor will be: Lmin = (Vin – VO)(DTs)/(2IO min) = (5 – 2.8)(0.56 x 3.3 µs)/(2 x 1.4 A) = 1.45 µH Coilcraft’s U6904, or an equivalent, provides a surface mount 1.5 µH choke which is rated for for full load current. 4. Output capacitor selection Vripple ≈ ∆ IL x ESR, where ESR is the equivalent series resistance of the output capacitance. Therefore: ESRmax = Vripple/∆ IL = 0.01 x 2.8 V/1.4 A = 0.02 Ω maximum The AVX TPS series of tantalum chip capacitors may be chosen. Or OSCON capacitors may be used if leaded parts are acceptable. In this case, the output capacitance consists of two parallel 820 µF, 4.0 V capacitors. Each capacitor has a maximum specified ESR of 0.012 Ω. 5. Input Filter As with all buck converters, input current is drawn in pulses. In this case, the current pulses may be 14 A peak. If a 1.5 µH choke is used, two parallel OSCON 150 µF, 16 V capacitors will provide a filter cutoff frequency of 7.5 kHz. 6. Feedback Loop Compensation The corner frequency of the output filter with L = 1.5 µH and Co = 1640 µF is 3.2 kHz. In addition, the ESR of each output capacitor creates a zero at: fz = 1/(2π C ESR) = 1/(2π x 820 µF x 0.012) = 16.2 kHz The dc gain of the PWM is: Gain = Vin/Vpp = 5/1 = 5.0. Where Vpp is the peak–to–peak sawtooth voltage across the internal timing capacitor. In order to make the feedback loop as responsive as possible to load changes, choose the unity gain frequency to be 10% of the switching frequency, or 30 kHz. Plotting the PWM gain over frequency, at a frequency of 30 kHz the gain is about –16.5 dB = 0.15. Therefore, to have a 30 kHz unity gain loop, the error amplifier gain at 30 kHz should be 1/0.15 = 6.7. Choose a design phase margin for the loop of 60 °. Also, choose the error amp type to be an integrator for best dc regulation performance. The phase boost needed by the error amplifier is then 60 ° for the desired phase margin. Then, the following calculations can be made: k = tan [Boost/2 + 45 °] = tan [60/2 + 45] = 3.73 Error Amp zero freq = fc/K = 30 kHz/3.73 = 8.0 kHz Error Amp pole freq = Kfc = 3.73 x 30 kHz = 112 kHz R2 = Error Amp Gain/Gm = 6.7/800 µ = 8.375 k – use an 8.2 k standard value C16 = 1/(2 π R2 fz) = 1/(2π x 8.2 k x 8.0 kHz) = 2426 pF – use 2200 pF C17 = 1/(2 π R2 fp) = 1/(2π x 8.2 k x 112 kHz) = 173 pF – use 100 pF The complete design is shown in Figure 13. The PC board top and bottom views are shown in Figures 17 and 18. Figure 16. Voltage Coupling Through Miller Capacitance |
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