1

®

FN8199.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-352-6832

XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved

All other trademarks mentioned are the property of their respective owners.

PRELIMINARY

X9438

Programmable Analog

Dual Digitally Controlled Potentiometer

(XDCP™) with Operational Amplifier

FEATURES

• Two CMOS voltage operational amplifiers

• Two digitally controlled potentiometers

• Can be combined or used separately

•Amplifiers:

—Low voltage operation

—V+/V- = ±2.7V to ±5.5V

—Rail-to-rail CMOS performance

—1MHz gain bandwidth product

• Digitally controlled potentiometers

—Dual 64 tap potentiometers

—2-wire serial interface

DESCRIPTION

The X9438 is a monolithic CMOS IC that incorporates

two operational amplifiers and two nonvolatile digitally

controlled potentiometers. The amplifiers are CMOS

differential input voltage operational amplifiers with

near rail-to-rail outputs. All pins for the two amplifiers

are brought out of the package to allow combining

them with the potentiometers, or using them as com-

plete stand-alone amplifiers.

The digitally controlled potentiometers consist of a

series string of 63 polycrystalline resistors that behave

as standard integrated circuit resistors. The two-wire

serial port, common to both pots, allows the user to

program the connection of the wiper output to any of

the resistor nodes in the series string. The wiper posi-

tion is saved in the on board E2 memory to allow for

nonvolatile restoration of the wiper position.

A wide variety of applications can be implemented

using the potentiometers and the amplifiers. A typical

application is to implement the amplifier as a wiper

buffer in circuits that use the potentiometer as a voltage

reference. The potentiometer can also be combined

with the amplifier yielding a digitally programmable gain

amplifier or programmable current source.

BLOCK DIAGRAM

Control and

SCL

SDA

A3

A2

A1

A0

+

–

Memory

WP

V+

V-

+

–

WCR1

WCR0

Data Sheet

March 11, 2005

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