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X9438WP24I Datasheet(PDF) 11 Page - Intersil Corporation |
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X9438WP24I Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 18 page  11 FN8199.0 March 11, 2005 ENDURANCE AND DATA RETENTION CAPACITANCE POWER-UP TIMING AND SEQUENCE A.C. TEST CONDITIONS Note: (1) Applicable to recall and power consumption applications EQUIVALENT A.C. LOAD CIRCUIT SPICE Macro Model Parameter Min. Unit Minimum endurance 100,000 Data changes per bit per register Data retention 100 Years Symbol Test Typical Unit Test Conditions CI/O Input/output capacitance (SDA) 8 pF VI/O = 0V CIN Input capacitance (A0, A1, A2, A3, and SCL) 6 pF VIN = 0V CL | CH | CW Potentiometer capacitance 10/10/25 pF See SPICE Model Power-up sequence(1): (1) VCC (2) V+ and V- Power-down sequence: no limitation Input pulse levels VCC x 0.1 to VCC x 0.9 Input rise and fall times 10ns Input and output timing level VCC x 0.5 5V 1533 Ω 100pF SDA Output 2.7V 100pF CW RTOTAL RH RL CH RW CL X9438 |
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