1

®

FN8200.0

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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X9440

Mixed Signal with SPI Interface

Dual Digitally Controlled Potentiometer

(XDCP™) & Voltage Comparator

FEATURES

• Two digitally controlled potentiometers and two

voltage comparators in one package

• SPI serial interface

• Register oriented format

—Direct read/write wiper position

—Store as many as four positions per pot

• Fast response comparator

• Enable, latch, or shutdown comparator outputs

through the ACR

• Auto-recall of WCR and ACR data from R0

• Hardware write protection, WP

• Separate analog and digital/system supplies

• Direct write cell

—Endurance–100,000 data changes per bit per

register

—Register data retention–100 years

• 16-bytes of EEPROM memory

• Power saving feature and low noise

• Two 10k

Ω or two 2.5kΩ potentiometers

• Resolution: 64 taps each pot

• 24-lead TSSOP and 24-Lead SOIC packages

DESCRIPTION

The X9440 integrates two non volatile digitally con-

trolled potentiometers (XDCP) and two voltage com-

parators on a CMOS monolithic microcircuit.

The X9440 contains two resistor arrays, each com-

posed of 63 resistive elements. Between each ele-

ment and at either end are tap points accessible to the

wiper elements. The position of the wiper element on

the array is controlled by the user through the SPI

serial bus interface.

Each potentiometer has an associated voltage com-

parator. The comparator compares the external input

put voltage level to a logic high or low.

Each resistor array and comparator has associated

with it a wiper counter register (WCR), analog control

register (ACR), and eight 6 bit data registers that can

be directly written and read by the user. The contents

of the wiper counter register controls the position of

the wiper on the resistor array. The contents of the

analog control register controls the comparator and its

output. The potentiometer is programmed with a SPI

serial interface.

BLOCK DIAGRAM

Interface

and

Control

Circuitry

SCK

S0

SI

A1

CS

HOLD

WP

+

–

A0

Data Sheet

March 28, 2005