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X9525 Datasheet(PDF) 9 Page - Intersil Corporation |
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X9525 Datasheet(HTML) 9 Page - Intersil Corporation |
9 / 26 page 9 FN8210.0 March 10, 2005 It should be noted that when reading out the data byte for DCP1 (100 Tap), the upper most significant bit is an “unknown”. For DCP2 (256 Tap) however, all bits of the data byte are relevant (See Figure 10). 2kbit EEPROM ARRAY Operations on the 2kbit EEPROM Array, consist of either 1, 2 or 3 byte command sequences. All operations on the EEPROM must begin with the Device Type Identifier of the Slave Address set to 1010A000. A Read or Write to the EEPROM is selected by setting the LSB of the Slave Address to the appropriate value R/W (Read = “1”, Write = “0”). In some cases when performing a Read or Write to the EEPROM, an Address Byte may also need to be specified. This Address Byte can contain the values 00h to FFh. EEPROM Byte Write In order to perform an EEPROM Byte Write operation to the EEPROM array, the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” on page 12.) For a write operation, the X9525 requires the Slave Address Byte and an Address Byte. This gives the master access to any one of the words in the array. After receipt of the Address Byte, the X9525 responds with an ACKNOWLEDGE, and awaits the next eight bits of data. After receiving the 8 bits of the Data Byte, it again responds with an ACKNOWLEDGE. The master then terminates the transfer by generating a STOP condition, at which time the X9525 begins the internal write cycle to the nonvolatile memory (See Figure 11). During this internal write cycle, the X9525 inputs are disabled, so it does not respond to any requests from the master. The SDA output is at high impedance. A write to a region of EEPROM memory which has been protected with the Block-Lock feature (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” on page 12.), suppresses the ACKNOWLEDGE bit after the Address Byte. EEPROM Page Write In order to perform an EEPROM Page Write operation to the EEPROM array, the Write Enable Latch (WEL) bit of the CONSTAT Register must first be set (See “BL1, BL0: Block Lock protection bits - (Nonvolatile)” on page 12.) The X9525 is capable of a page write operation. It is initi- ated in the same manner as the byte write operation; but instead of terminating the write cycle after the first data byte is transferred, the master can transmit an unlimited number of 8-bit bytes. After the receipt of each byte, the X9525 responds with an ACKNOWLEDGE, and the address is internally incremented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to ‘0’ on the same page. For example, if the master writes 12 bytes to the page starting at location 11 (decimal), the first 5 bytes are writ- ten to locations 11 through 15, while the last 7 bytes are written to locations 0 through 6. Afterwards, the address counter would point to location 7. If the master supplies more than 16 bytes of data, then new data overwrites the previous data, one byte at a time (See Figure 13). The master terminates the Data Byte loading by issuing a STOP condition, which causes the X9525 to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 12 for the address, ACKNOWL- EDGE, and data transfer sequence. S t a r t S t o p Slave Address Address Byte Data (n) A C K A C K A C K SDA Bus Signals from the Slave Signals from the Master Data (1) A C K (2 < n < 16) Figure 12. EEPROM Page Write Operation 1 01 0 0 0 0 A 0 X9525 |
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