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X9448WV24I Datasheet(PDF) 4 Page - Intersil Corporation |
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X9448WV24I Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 19 page  4 FN8201.0 April 18, 2005 Voltage Comparator The comparator compares the wiper voltage VW with the external input voltage VNI. The comparator and its logic level output are controlled by the Shutdown, Latch, and Enable bits of the analog control register (ACR). Enable connects the comparator output to the VOUT pin, Latch memorizes the output logic state, and Shutdown removes the analog section supply voltages to save power. The analog control register is pro- grammed using the two wire serial interface. The ACR may be written directly, or it can be changed by transferring the contents of one of four associated data registers into the ACR. These data registers and the ACR may be read and written by the host system. INSTRUCTIONS AND PROGRAMMING Device Addressing Following a start condition the master must output the address of the slave it is accessing. The most signifi- cant four bits of the slave address are the device type identifier (refer to Figure 1 below). For the X9448 this is fixed as 0101[B]. Figure 1. Address/Identification Byte Format The next four bits of the slave address are the device address. The physical device address is defined by the state of the A0 - A3 inputs. The X9448 compares the serial data stream with the address input state; a successful compare of all four address bits is required for the X9448 to respond with an acknowledge. The A0 - A3 inputs can be actively driven by CMOS input signals or tied to VCC or VSS. Acknowledge Polling The disabling of the inputs, during the internal nonvol- atile write operation, can be used to take advantage of the typical 5ms EEPROM write cycle time. Once the stop condition is issued to indicate the end of the non- volatile write command the X9448 initiates the internal write cycle. ACK polling (Flow 1) can be initiated immediately. This involves issuing the start condition followed by the device slave address. If the X9448 is still busy with the write operation no ACK will be returned. If the X9448 has completed the write opera- tion an ACK will be returned and the master can then proceed with the next operation. Flow 1. ACK Polling Sequence Instruction Structure The byte following the address contains the instruction and register pointer information. The four most signifi- cant bits are the instruction. The next four bits point to one of two pots or one of two voltage comparators and when applicable they point to one of four associated registers. The format is shown below in Figure 2. Figure 2. Instruction Byte Format The four high order bits define the instruction. The next two bits (R1 and R0) select one of the four regis- ters that is to be acted upon when a register oriented instruction is issued. The last two bits (P1 and P0) select which one of the two potentiometers or which one of the two voltage comparators is to be affected by the instruction. Four of the nine instructions end with the transmission of the instruction byte. The basic sequence is illus- trated in Figure 3. These two-byte instructions exchange data between the wiper counter register or analog control register and one of the data registers. A transfer from a data register to a wiper counter register 1 00 A3 A2 A1 A0 Device Type Identifier Device Address 1 Nonvolatile Write Command Completed Enter ACK Polling Issue START Issue Slave Address ACK Returned? Further Operation Issue Instruction PROCEED Issue STOP NO YES YES PROCEED Issue STOP NO I1 I2 I3 I0 R1 R0 P1 P0 WCR and ACR Select Register Select Instructions X9448 |
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