X40231S169-A datasheet(10/36 Pages) INTERSIL

Part #	X40231S169-A

Description	Triple Voltage Monitors, POR, 2 kbit EEPROM MEMORY, and Single/Dual DCP

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Manufacturer	INTERSIL [Intersil Corporation]

Direct Link	http://www.intersil.com/cda/home

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10 / 36 page

10

FN8115.0

April 11, 2005

Depending upon the operation to be performed on

each of these individual parts, a 1, 2 or 3 Byte protocol

is used. All operations however must begin with the

Slave Address Byte being issued on the SDA pin. The

Slave address selects the part of the X4023x to be

addressed, and specifies if a Read or Write operation

is to be performed.

It should be noted that in order to perform a write oper-

ation to either a DCP or the EEPROM array, the Write

Enable Latch (WEL) bit must first be set (See “BL1,

BL0: Block Lock protection bits - (Nonvolatile)” on

page 18.)

Slave Address Byte

Following a START condition, the master must output

a Slave Address Byte (Refer to Figure 4). This byte

consists of three parts:

—The Device Type Identifier which consists of the most

significant four bits of the Slave Address (SA7 - SA4).

The Device Type Identifier must always be set to 1010

in order to select the X4023x.

—The next three bits (SA3 - SA1) are the Internal Device

Address bits. Setting these bits to 000 internally

selects the EEPROM array, while setting these bits to

111 selects the DCP structures in the X4023x. The CR

Register may be selected using the Internal Device

Address 010.

—The Least Significant Bit of the Slave Address (SA0)

Byte is the R/W bit. This bit defines the operation to be

performed on the device being addressed (as defined

in the bits SA3 - SA1). When the R/W bit is “1”, then a

READ operation is selected. A “0” selects a WRITE

operation (Refer to Figure 4)

Nonvolatile Write Acknowledge Polling

After a nonvolatile write command sequence (for either

the EEPROM array, the Non Volatile Memory of a DCP

(NVM), or the CR Register) has been correctly issued

(including the final STOP condition), the X4023x ini-

tiates an internal high voltage write cycle. This cycle

typically requires 5 ms. During this time, no further

Read or Write commands can be issued to the device.

Write Acknowledge Polling is used to determine when

this high voltage write cycle has been completed.

To perform acknowledge polling, the master issues a

START condition followed by a Slave Address Byte.

The Slave Address issued must contain a valid Inter-

nal Device Address. The LSB of the Slave Address

(R/W) can be set to either 1 or 0 in this case. If the

device is still busy with the high voltage cycle then no

ACKNOWLEDGE will be returned. If the device has

completed the write operation, an ACKNOWLEDGE

will be returned and the host can then proceed with a

read or write operation. (Refer to Figure 5)

DIGITALLY CONTROLLED POTENTIOMETERS

DCP Functionality

The X4023x includes one or two independent resistor

arrays. For the 64, 100 or 256 tap XDCPs, these

arrays respectively contain 63, 99 discrete resistive

segments that are connected in series. (the 256 tap

resistor achieves an equivalent end to end resistance.)

The physical ends of each array are equivalent to the

fixed terminals of a mechanical potentiometer. At one

end of the resistor array the terminal connects to the

RHx pin (x = 0,1,2).The other end of the resistor array

is connected to VSS inside the package.

SA6

SA7

SA5

SA3

SA2

SA1

SA0

DEVICE TYPE

IDENTIFIER

READ /

SA4

Internal Address

(SA3 - SA1)

Internally Addressed

Device

000

EEPROM Array

010

CR Register

111

DCP

Bit SA0

Operation

0WRITE

1

READ

R/W

Figure 4.

Slave Address Format

101

0

WRITE

ADDRESS

INTERNAL

DEVICE

X40231, X40233, X40235, X40237, X40239

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