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X40626S14-4.5A Datasheet(PDF) 10 Page - Intersil Corporation |
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X40626S14-4.5A Datasheet(HTML) 10 Page - Intersil Corporation |
10 / 22 page 10 FN8119.0 March 28, 2005 Figure 9. Page Write Operation Figure 10. Writing 12 bytes to a 64-byte page starting at location 60 (Wrap around). The master terminates the Data Byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. See Figure 9 for the address, acknowledge, and data transfer sequence. Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Acknowledge Polling The disabling of the inputs during nonvolatile cycles can be used to take advantage of the typical 5mS write cycle time. Once the stop condition is issued to indi- cate the end of the master’s byte load operation, the device initiates the internal nonvolatile cycle. Acknowl- edge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the nonvolatile cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. Refer to the flow chart in Figure 11. S T A R T S T O P A C K A C K A C K A C K A C K Data (0) (n) 0 S P Data 1 0 1 0 (I ≤ n ≤ 63) Signals from the Master SDA Bus Signals from the Slave Slave Address Byte 1 Word Address Byte 0 Word Address 0 S1 S0 address address 60 4 Bytes 63 8 Bytes address = 7 address pointer ends here Addr = 8 X40626 |
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