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X55060 Datasheet(PDF) 1 Page - Intersil Corporation

Part # X55060
Description  Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X55060 Datasheet(HTML) 1 Page - Intersil Corporation

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1
®
FN8133.0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
PRELIMINARY
X55060
64K
Dual Voltage Monitor with Integrated
System Battery Switch and EEPROM
FEATURES
• Dual voltage monitoring
• Active high and active low reset outputs
• Four standard reset threshold voltages
(4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6)
—User programmable thresholds
• Lowline Output — Zero delayed POR
• Reset signal valid to VCC = 1V
• System battery switch-over circuitry
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<30µA max standby current, watchdog off
• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect none(0), or all of EEPROM array with
programmable Block Lockprotection
—In circuit programmable ROM mode
• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 10MHz SPI interface modes (0,0 & 1,1)
• 2.7V to 5.5V power supply operation
• Available packages — 20-lead TSSOP
DESCRIPTION
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
BLOCK DIAGRAM
Watchdog
Timer Reset
Data
Register
Command
Decode, Test
& Control
Logic
SI
SO
SCK
CS
VCC
Reset &
Watchdog
Timebase
Power-on,
Generation
VCC Monitor
+
-
RESET
Reset
Low Voltage
Status
Register
Protect Logic
EEPROM Array
Watchdog Transition
Detector
WP
512 X 128
VTRIP1
Logic
V2 Monitor
+
-
VTRIP2
Logic
System
Switch
RESET/MR
LOWLINE
V2FAIL
V2MON
VBATT
VOUT
(V1MON)
Battery
WDO
BATT-ON
VOUT
VOUT
Data Sheet
March 28, 2005


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