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X40021S14-C Datasheet(PDF) 11 Page - Intersil Corporation |
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X40021S14-C Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 24 page 11 FN8112.0 March 28, 2005 Figure 10. Byte Write Sequence Stops and Write Modes Stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte plus the subsequent ACK signal. If a stop is issued in the middle of a data byte, or before 1 full data byte plus its associated ACK is sent, then the device will reset itself without performing the write. The contents of the array will not be effected. Acknowledge Polling The disabling of the inputs during high voltage cycles can be used to take advantage of the typical 5ms write cycle time. Once the stop condition is issued to indi- cate the end of the master’s byte load operation, the device initiates the internal high voltage cycle. Acknowledge polling can be initiated immediately. To do this, the master issues a start condition followed by the Slave Address Byte for a write or read operation. If the device is still busy with the high voltage cycle then no ACK will be returned. If the device has completed the write operation, an ACK will be returned and the host can then proceed with the read or write operation. See Figure 11. Serial Read Operations Read operations are initiated in the same manner as write operations with the exception that the R/W bit of the Slave Address Byte is set to one. Figure 11. Acknowledge Polling Sequence S t a r t S t o p Slave Address Byte Address Data A C K A C K A C K SDA Bus Signals from the Slave Signals from the Master 0 ACK Returned? Issue Slave Address Byte (Read or Write) Byte Load Completed by Issuing STOP. Enter ACK Polling Issue STOP Issue START NO YES High Voltage Cycle Complete. Continue Command Sequence? Issue STOP NO Continue Normal Read or Write Command Sequence PROCEED YES X40020, 40021 |
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