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X40434S14I-A Datasheet(PDF) 2 Page - Intersil Corporation |
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X40434S14I-A Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 24 page 2 FN8251.0 July 29, 2005 BLOCK DIAGRAM *Voltage monitor requires Vcc to operate. Others are independent of Vcc. PIN CONFIGURATION V3FAIL V2FAIL WDO MR LOWLINE RESET RESET X40430/34 X40431/35 V3 Monitor Logic V2 Monitor Logic Fault Detection Register Status Register EEPROM Array Data Register Command Decode Test & Control Logic Power-on, Manual Reset Low Voltage Reset Generation VCC Monitor Logic V3MON V2MON SDA WP SCL VCC (V1MON) + - + - Watchdog and Reset Logic VTRIP3 + - VTRIP2 VTRIP1 *X40430, X40431= VCC or V2MON* V2MON X40434, X40435 =VCC Device Expected System Voltages Vtrip1(V) Vtrip2(V) Vtrip3(V) POR (system) X40430, X40431 -A -B -C 5V; 3V or 3.3V; 1.8V 5V; 3V; 1.8V 3.3V; 2.5V; 1.8V 2.0–4.75* 4.55–4.65* 4.35–4.45* 2.95–3.05* 1.70–4.75 2.85–2.95 2.55–2.65 2.15–2.25 1.70–4.75 1.65–1.75 1.65–1.75 1.65–1.75 RESET = X40430 RESET = X40431 X40434, X40435 -A -B -C 5V; 3.3V; 1.5V 5V; 3V or 3.3V; 1.5V 5V; 3 or 3.3V; 1.2V 2.0–4.75* 4.55–4.65* 4.55–4.65* 4.55–4.65* 0.90–3.50* 1.25–1.35* 1.25–1.35* 0.95–1.05* 1.70–4.75 3.05–3.15 2.85–2.95 2.85–2.95 RESET = X40434 RESET = X40435 V3MON VSS VCC SDA SCL 3 2 4 1 12 13 11 14 LOWLINE NC RESET 7 6 5 8 9 10 V2MON MR WP 3 2 4 1 12 13 11 14 7 6 5 8 9 10 V3FAIL WDO V2FAIL V3MON VCC SDA SCL WP V3FAIL WDO VSS LOWLINE NC RESET V2MON MR V2FAIL X40430, X40434 X40431, X40435 14-Pin SOIC, TSSOP 14-Pin SOIC, TSSOP PIN DESCRIPTION Pin Name Function 1V2FAIL V2 Voltage Fail Output. This open drain output goes LOW when V2MON is less than VTRIP2 and goes HIGH when V2MON exceeds VTRIP2. There is no power-up reset delay circuitry on this pin. 2V2MON V2 Voltage Monitor Input. When the V2MON input is less than the VTRIP2 voltage, V2FAIL goes LOW. This input can monitor an unregulated power supply with an external resistor divider or can monitor a second power supply with no external components. Connect V2MON to VSS or VCC when not used. The V2MON comparator is supplied by V2MON (X40430, X40431) or by the VCC input (X40434, X40435). 3LOWLINE Early Low VCC Detect. This CMOS output signal goes LOW when VCC < VTRIP1 and goes high when VCC > VTRIP1. 4NC No connect. X40430, X40431, X40434, X40435 |
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