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X80012Q32I Datasheet(PDF) 4 Page - Intersil Corporation

Part # X80012Q32I
Description  Penta-Power Sequence Controller with Hot swap and System Management
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Manufacturer  INTERSIL [Intersil Corporation]
Direct Link  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

X80012Q32I Datasheet(HTML) 4 Page - Intersil Corporation

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4
FN8149.0
January 13, 2005
VOL
Output LOW Voltage
(RESET, RESET, V1GOOD, V2GOOD,
V3GOOD, V4GOOD, FAR, PWRGD)
IOL = 4.0mA
(VEE + 2.7 to VEE + 5.5V)
IOL = 2.0mA
(VEE + 2.7 to VEE + 3.6V)
VEE + 0.4
V
COUT(1)
Output Capacitance
(RESET, V1GOOD, V2GOOD, V3GOOD,
V4GOOD, FAR)
VOUT = 0V
8
pF
CIN(1)
Input Capacitance (MRH, MRC)
VIN = 0V
6
pF
VOC
Over-current threshold
VOC = VSENSE - VEE
45
50
55
mV
VOCI
Over-current threshold (Insertion)
VOC = VSENSE - VEE
PWRGD = HIGH
Initial Power Up condition
135
150
165
mV
VOVR
Overvoltage threshold (rising)
X80010, X80012
X80011, X80013
Referenced to VEE
3.85
3.49
3.90
3.54
3.95
3.59
V
VOVH
Overvoltage hysteresis
Referenced to VEE
12
18
24
mV
VUV1H
Undervoltage 1 hysteresis
Referenced to VEE
BATT-ON = VEE
12
18
24
mV
VUV1F
Undervoltage 1 threshold (falling)
2.16
2.21
2.26
V
VUV2H
Undervoltage 2 hysteresis
Referenced to VEE
BATT-ON = VRGO
12
18
24
mV
VUV2F
Undervoltage 2 threshold (falling)
1.68
1.73
1.78
V
VDRAINF
Drain sense voltage threshold
(falling)
Referenced to VEE
0.9
1
1.1
V
VDRAINR
Drain sense voltage threshold
(rising)
Referenced to VEE
1.2
1.3
1.4
V
VTRIP1
EN1 Trip Point Voltage
Referenced to VEE
2.25
2.5
2.75
V
VTRIP2
EN2 Trip Point Voltage
Referenced to VEE
2.25
2.5
2.75
V
VTRIP3
EN3 Trip Point Voltage
Referenced to VEE
2.25
2.5
2.75
V
VTRIP4
EN4 Trip Point Voltage
Referenced to VEE
2.25
2.5
2.75
V
AC CHARACTERISTICS
tFOC
Sense High to Gate Low
1.5
2.5
3.5
µs
tFUV
Under Voltage conditions to Gate Low
0.5
1.0
1.5
µs
tFOV
Overvoltage Conditions to Gate Low
1.0
1.5
2
µs
tVFR
Overvoltage/undervoltage failure recovery time
to Gate =1V.
VDD does not drop below 3V, No
other failure conditions.
1.2
1.6
2
µs
tBATT_ON Delay BATT_ON Valid
100
ns
tMRC
Minimum time high for reset valid on the MRC
pin
5
µs
tMRH
Minimum time high for reset valid on the MRH
pin
5
µs
tMRCE
Delay from MRC enable to PWRGD HIGH
No Load
1.0
1.6
µs
tMRCD
Delay from MRC disable to PWRGD LOW
Gate is On, No Load
200
400
µs
tMRHE
Delay from MRH enable to Gate Pin LOW
IGATE = 60µA, No Load
1.0
1.6
2.4
µs
tMRHD
Delay from MRH disable to GATE reaching 1V IGATE = 60µA, No Load
1.8
2.6
µs
Electrical Specifications
(Standard Settings)
Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
X80010, X80011, X80012, X80013


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