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X95820WV14IZ-2.7 Datasheet(PDF) 2 Page - Intersil Corporation |
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X95820WV14IZ-2.7 Datasheet(HTML) 2 Page - Intersil Corporation |
2 / 12 page 2 FN8212.1 September 26, 2005 Block Diagram RH1 WR1 RW1 RL1 RH0 WR0 RW0 RL0 Power-up, Interface, Control and Status Logic Non-Volatile Registers 2-wire Interface SDA SCL A2 A1 A0 WP GND VCC PiN Descriptions PIN SYMBOL DESCRIPTION 1VCC Power supply pin 2WP Hardware write protection pin. Active low. Prevents any “Write” operation of the 2-wire interface. 3 RH0 “High” terminal of DCP0 4 RL0 “Low” terminal of DCP0 5 RW0 “Wiper” terminal of DCP0 6 A2 Device address for the 2-wire interface 7 SCL 2-wire interface clock 8 SDA Serial data I/O for the 2-wire interface 9 GND Ground 10 RW1 “Wiper” terminal of DCP1 11 RL1 “Low” terminal of DCP1 12 RH1 “High” terminal of DCP1 13 A0 Device address for the 2-wire interface 14 A1 Device address for the 2-wire interface X95820 |
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