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X95840UV20IZ-2.7 Datasheet(PDF) 4 Page - Intersil Corporation |
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X95840UV20IZ-2.7 Datasheet(HTML) 4 Page - Intersil Corporation |
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4 / 13 page  4 FN8213.1 September 27, 2005 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX UNITS ICC1 VCC supply current (Volatile write/read) fSCL = 400kHz; SDA = Open; (for 2-Wire, Active, Read and Volatile Write States only) 1mA ICC2 VCC supply current (nonvolatile write) fSCL = 400kHz; SDA = Open; (for 2-Wire, Active, Nonvolatile Write State only) 3mA ISB VCC current (standby) VCC = +5.5V, 2 Wire Interface in Standby State 5 µA VCC = +3.6V, 2 Wire Interface in Standby State 2 µA ILkgDig Leakage current, at pins A0, A1, A2, SDA, SCL, and WP pins Voltage at pin from GND to VCC -10 10 µA tDCP (Note 15) DCP wiper response time SCL falling edge of last bit of DCP Data Byte to wiper change 1µs Vpor Power-on recall voltage Minimum VCC at which memory recall occurs 1.8 2.6 V VccRamp VCC ramp rate 0.2 V/ms tD (Note 15) Power up delay VCC above Vpor, to DCP Initial Value Register recall completed, and 2-Wire Interface in standby state 3ms EEPROM SPECS EEPROM Endurance 150,000 Cycles EEPROM Retention Temperature ≤ 75°C 50 Years SERIAL INTERFACE SPECS VIL WP, A2, A1, A0, SDA, and SCL input buffer LOW voltage -0.3 0.3*Vcc V VIH WP, A2, A1, A0, SDA, and SCL input buffer HIGH voltage 0.7*Vcc Vcc+0.3 V Hysteresis (Note 15) SDA and SCL input buffer hysteresis 0.05* Vcc V VOL (Note 15) SDA output buffer LOW voltage, sinking 4 mA 00.4 V Cpin (Note 15) WP, A2, A1, A0, SDA, and SCL pin capacitance 10 pF fSCL SCL frequency 400 kHz tIN (Note 15) Pulse width suppression time at SDA and SCL inputs Any pulse narrower than the max spec is suppressed. 50 ns tAA (Note 15) SCL falling edge to SDA output data valid SCL falling edge crossing 30% of VCC, until SDA exits the 30% to 70% of VCC window. 900 ns tBUF (Note 15) Time the bus must be free before the start of a new transmission SDA crossing 70% of VCC during a STOP condition, to SDA crossing 70% of VCC during the following START condition. 1300 ns tLOW Clock LOW time Measured at the 30% of VCC crossing. 1300 ns tHIGH Clock HIGH time Measured at the 70% of VCC crossing. 600 ns tSU:STA START condition setup time SCL rising edge to SDA falling edge. Both crossing 70% of VCC. 600 ns tHD:STA START condition hold time From SDA falling edge crossing 30% of VCC to SCL falling edge crossing 70% of VCC. 600 ns X95840 |
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