5

3.2 Transmit Byte Clock

3.2.1 FULL- AND HALF-RATE MODE

Since the BBT3420 normally employs Double Data Rate

(DDR) timing, the local reference clock requirement is

lowered to 124.4-159.375MHz. The Transmit Byte Clock

(TBC) must be frequency-synchronous with the local

reference clock. For any channel set to Half-Rate Clock

Mode by the MDIO/MDC register 1F’h (for Clause 22) and/or

C008’h (for Clause 45), see Table 3-30, the TBC must be

provided at half the ref clock frequency, unless the TX_SDR

bit is set in the MDIO register C001’h (Clause 45, Table 3-

33) and/or 1D’h (Clause 22, Table 3-28).

3.2.2 SOURCE-CENTERED AND -SIMULTANEOUS

MODE

For ease of ASIC timing, the BBT3420 provides the option

for the TBC to be source-simultaneous or source-centered.

In source-simultaneous mode, the ASIC is not required to

adjust the TBC signal to the center of the data window. The

internal latch clock of the BBT3420 is set to +5 serial bit

times after the rising edge of the clock (TBC or RefClock)

when the chip is reset. In source-centered mode, the

BBT3420 expects stable data, with proper setup/hold time

with respect to the TBC from the ASIC. The specific clocking

mode is selectable by the MDIO/MDC register bit SC_TBC

at address 11’h in Clause 22 format, Table 3-16, and/or

C001’h in Clause 45 format, Table 3-33.

3.2.3 TRUNKING MODE

The TBC source for each channel is determined by the

trunking mode setting of the PSYNC pin. When trunking is

turned on (PSYNC high), all four channels are latched by the

Channel A TBC on pin TCA. In non-trunking mode, each

channel is latched with its corresponding TBC pin TC[A-D]

independently. Note that PSYNC will also force trunking of

the Receive Byte Clocks (see below). Alternatively, the

TC[A-D] inputs may be driven from a common source, such

as the local reference clock.

3.3 Transmit FIFO

A 4-byte-deep input FIFO is used to accommodate any TBC

or data drift. The initial pointer value is 2 bytes, which can

accommodate ±2 byte skew between channels, as well as

drift between the TBC and the reference clock. When the

FIFO depth is at one, the transmit data is ready for output on

the next TXC.

3.4 Serializer

The serializer accepts 10-bit transmission characters and

converts them from a parallel format to a serial bit stream at

2.488-3.1875Gbps. The system designer is expected to treat

such signals on the PCB as transmission lines and to use a

controlled impedance and suitable termination.

3.5 Pre-emphasis

In order to compensate for the loss of the high-frequency

signal components through PCB or cable, four levels of

programmable pre-emphasis have been added to all serial

transmit channels. This maximizes the data eye opening at

the receiver inputs and enhances the bit error rate

performance of the system. The MDIO Register at Address

1C’h (for Clause 22) and/or C005’h (for Clause 45) (see

Table 3-27) controls the level of pre-emphasis. Note that the

formula used to determine the pre-emphasis valuse is NOT

the same as that used in the IEEE 802.3ak-2004

specification for this parameter.

1

FD

X

X

/T/

K29.7

Terminate

1

3C

X

X

K28.1

Extra comma

1

5C

X

X

/F/

K28.2

Signal Ordered_Set marker

1

9C

X

X

/Q/

K28.4

Sequence Ordered_Set marker

1DC

X

X

K28.6

1

FC

X

X

K28.7

Repeat gives False Comma

1F7

X

X

K23.7

1

FE

X

X

/E/

K30.7

Error Code

1

(all others)

X

X

Invalid code

Error Code

NOTES:

1. If the XAUI_EN bit is set, the BBT3420 acts as though both the TRANS_EN and AKR_EN bits are set.

2. The XGMII IDLE character is set by the XGMII IDLE register, address 1B’h/C003’h (see Table 3-26), default value 07’h, combined with the K

bit (XGMII value 107’h).

TABLE 3-1. VALID 8B/10B ENCODER PATTERNS (Continued)

TRANSMITTING SERDES

NOTES and

DESCRIPTION

K-BIT

TD DATA

TRANS_EN

BIT (Note 1)

AKR_EN BIT

(Note 1)

SERIAL

CHARACTER

SERIAL

CODE

BBT3420