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PE3239 Datasheet(PDF) 9 Page - Peregrine Semiconductor Corp. |
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PE3239 Datasheet(HTML) 9 Page - Peregrine Semiconductor Corp. |
9 / 12 page Product Specification PE3239 Page 9 of 12 Document No. 70-0047-02 │ www.psemi.com ©2006 Peregrine Semiconductor Corp. All rights reserved. MSB (first in) (last in) LSB Table 7. Primary Register Programming Table 8. Enhancement Register Programming Interface Mode Enh R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0 Serial* 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 *Serial data clocked serially on Sclk rising edge while E_WR “low” and captured in secondary register on S_WR rising edge. Interface Mode Enh Reserved Reserved fp Output Power down Counter load MSEL output fc output Reserved Serial* 0 B0 B1 B2 B3 B4 B5 B6 B7 *Serial data clocked serially on Sclk rising edge while E_WR “high” and captured in the double buffer on E_WR falling edge. MSB (first in) (last in) LSB Figure 7. Serial Interface Mode Timing Diagram t DHLD t DSU t ClkH t ClkL t CWR t PW t WRC t EC t CE E_WR Sdata Sclk S_WR |
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