3

INDUSTRIALTEMPERATURERANGE

QS5919T

LOW SKEW TTL PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER

PIN DESCRIPTION

Pin Name

I/O

Description

I

Reference clock input

I

Reference clock input

REF_SEL

I

FREQ_SEL

I

VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency.

FEEDBACK

I

PLL feedback input which is connected to a user selected output pin. External feedback provides flexibility for different output

frequency relationships. See the Frequency Selection Table for more information.

O

Clock outputs

O

Clock output. Matched in frequency, but inverted with respect to Q.

2xQ

O

Clock output. Matched in phase, but frequency is double the Q frequency.

Q/2

O

Clock output. Matched in phase, but frequency is half the Q frequency.

LOCK

O

PLL lock indication signal. 1 indicates positive lock. 0 indicates that the PLL is not locked and outputs may not be synchronized to

the inputs.

OE/

RST

I

Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,

outputs are enabled.

PLL_EN

I

PLL enable. Enables and disables the PLL. Useful for testing purposes.

PE

I

When

PE is LOW, outputs are synchronized with the positive edge of SYNC. When HIGH, outputs are synchronized with the

negative edge of SYNC.

—

Power supply for output buffers.

—

Power supply for phase lock loop and other internal circuitries.

GND

—

Ground supply for output buffers.

AGND

—

Ground supply for phase lock loop and other internal circuitries.

OUTPUT FREQUENCY SPECIFICATIONS

Symbol

Description

– 55

– 70

– 100

– 133

– 160

Units

Max Frequency, 2xQ

55

70

100

133

160

MHz

27.5

35

50

66.5

80

MHz

Max Frequency, Q/2

13.75

17.5

25

33.25

40

MHz

Min Frequency, 2xQ

20

20

20

20

20

MHz

10

10

10

10

10

MHz

55

5

5

5

MHz