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TPS3307-18MDREP Datasheet(PDF) 2 Page - Texas Instruments |
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TPS3307-18MDREP Datasheet(HTML) 2 Page - Texas Instruments |
2 / 10 page TPS330718EP TRIPLE PROCESSOR SUPERVISORS SGLS140 – NOVEMBER 2002 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) The various supply voltage supervisors are designed to monitor the nominal supply voltage as shown in the following supply voltage monitoring table. SUPPLY VOLTAGE MONITORING DEVICE NOMINAL SUPERVISED VOLTAGE THRESHOLD VOLTAGE (TYP) DEVICE SENSE1 SENSE2 SENSE3 SENSE1 SENSE2 SENSE3 TPS3307-18 3.3 V 1.8 V User defined 2.93 V 1.68 V 1.25 V† † The actual sense voltage has to be adjusted by an external resistor divider according to the application requirements. During power-on, RESET is asserted when the supply voltage VDD becomes higher than 1.1 V. Thereafter, the supply voltage supervisor monitors the SENSEn inputs and keeps RESET active as long as SENSEn remain below the threshold voltage VIT+. An internal timer delays the return of the RESET output to the inactive state (high) to ensure proper system reset. The delay time, td typ = 200 ms, starts after all SENSEn inputs have risen above the threshold voltage VIT+. When the voltage at any SENSE input drops below the threshold voltage VIT–, the RESET output becomes active (low) again. The TPS3307-18 incorporates a manual reset input, MR. A low level at MR causes RESET to become active. In addition to the active-low RESET output, the TPS3307-18 includes an active-high RESET output. The device is available in a standard 8-pin SO package, and is characterized for operation over a temperature range of –55 °C to 125°C. ORDERING INFORMATION TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING –55 °C to 125°C Small Outline (D) Tape and Reel TPS3307-18MDREP 30718E ‡ Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION/TRUTH TABLES MR SENSE1>VIT1 SENSE2>VIT2 SENSE3>VIT3 RESET RESET L X X X L H H 0 0 0 L H H 0 0 1 L H H 0 1 0 L H H 0 1 1 L H H 1 0 0 L H H 1 0 1 L H H 1 1 0 L H H 1 1 1 H L X = Don’t care |
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