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A6801 Datasheet(PDF) 4 Page - Allegro MicroSystems |
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A6801 Datasheet(HTML) 4 Page - Allegro MicroSystems |
4 / 12 page 4 Worcester, Massachusetts 01615-0036 (508) 853-5000 115 Northeast Cutoff, Box 15036 www.allegromicro.com A6800/A6801 DABiC-5 Latched Sink Drivers Timing Requirements and Specifications (Logic Levels are VDD and Ground) NOTE: Information present at an input is transferred to its latch when the STROBE is high. A high CLEAR input will set all latches to the output off condition regardless of the data or STROBE input levels. A high Key Description Time (ns) A Minimum data active time before Strobe enabled (Data Set-Up Time) 25 B Minimum data active time after Strobe disabled (Data Hold Time) 25 C Minimum Strobe pulse width 50 D Maximum time between Strobe activation and transition from output on to output off* 500 E Minimum time between Strobe activation and transition from output off to output on* 500 F Maximum time between Output Enable activation and transition from output on to output off* 500 G Minimum time between Output Enable activation and transition from output off to output on* 500 H Minimum Clear pulse width 50 I Minimum data pulse width 100 CLEAR STROBE OUTPUT ENABLE INN OUTN A C BC B G D E H A C B I E G F *Conditions for output transition testing are: VDD = 50 V, VCC = 5 V, R1 = 500 Ω, C1 ≤ 30 pF. OUTPUT ENABLE will set all outputs to the off con- tdition, regardless of any other input conditions. When the OUTPUT ENABLE is low, the outputs depend on the state of their respective latches. |
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