A6832 datasheet(3/7 Pages) ALLEGRO

Part #	A6832

Description	DABiC-5 32-Bit Serial Input Latched Sink Drivers

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Manufacturer	ALLEGRO [Allegro MicroSystems]

Direct Link	http://www.allegromicro.com

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Worcester, Massachusetts 01615-0036 (508) 853-5000

115 Northeast Cutoff, Box 15036

www.allegromicro.com

A6832

DABiC-5 32-Bit Serial-Input Latched Sink Drivers

ELECTRICAL CHARACTERISTICS1 Unless otherwise noted: TA = 25°C, logic supply operating voltage Vdd= 3.0 V to 5.5 V

Characteristic

Symbol

Test Conditions

Vdd = 3.3 V

Vdd = 5 V

Units

Min.

Typ.

Max.

Min.

Typ.

Max.

Output Leakage Current

ICEX

VOUT = 40 V

–

10

–

10

μA

Collector–Emitter

Saturation Voltage

VCE(SAT)

IOUT = 50 mA

–

275

–

275

mV

IOUT = 100 mA

–

550

–

550

mV

Input Voltage

VIN(1)

2.2

–

3.3

–

V

VIN(0)

–

1.1

–

1.7

V

Input Current

IIN(1)

VIN = VDD

–

< 0.01

1.0

–

< 0.01

1.0

μA

IIN(0)

VIN = 0 V

–

< –0.01

–1.0

–

< –0.01

–1.0

μA

Serial Data Output Voltage

VOUT(1)

IOUT = –200 μA

2.8

3.05

–

4.5

4.75

–

V

VOUT(0)

IOUT = 200 μA

–

0.15

0.3

–

0.15

0.3

V

Maximum Clock Fre-

quency2

fc

10

–

10

–

MHz

Logic Supply Current

IDD(1)

One output on, IOUT = 100 mA

–

6.0

–

6.0

mA

IDD(0)

All outputs off

–

100

–

100

μA

Output Enable-to-Output

Delay

tdis(BQ)

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

ten(BQ)

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

Strobe-to-Output Delay

tp(STH-QL)

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

tp(STH-QH)

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

Output Fall Time

tf

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

Output Rise Time

tr

VCC = 50V, R1 = 500 Ω, C1≤30pF

–

1.0

–

1.0

μs

Clock-to-Serial Data Out Delay

tp(CH-SQX)

IOUT = ±200 μA

–

50

–

50

–

ns

1Positive (negative) current is deﬁned as conventional current going into (coming out of) the speciﬁed device pin.

2Operation at a clock frequency greater than the speciﬁed minimum value is possible but not warranteed.

L = Low Logic Level

H = High Logic Level

X = Irrelevant

P = Present State

R = Previous State

Serial

Shift Register Contents

Serial

Latch Contents

Output

Output Contents

Data

Clock

Data

Strobe

Enable

Input

Input I1

I2

I3

...

IN-1 IN

Output

Input

I1

I2

I3

...

IN-1 IN

Input

I1 I2 I3 ... IN-1 IN

HH

R1 R2 ...

RN-2 RN-1

RN-1

LL

R1 R2 ...

RN-2 RN-1

RN-1

XR1 R2 R3 ...

RN-1 RN

RN

XXX...

X

L

R1 R2 R3 ...

RN-1 RN

P1 P2 P3 ...

PN-1 PN

PN

HP1 P2 P3 ...

PN-1 PN

HP1 P2 P3 ... PN-1 PN

X

...

X

L

H

... H

H

Truth Table

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