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IDT82V2082 Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT82V2082 Datasheet(HTML) 10 Page - Integrated Device Technology |
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10 / 79 page  10 INDUSTRIAL TEMPERATURE RANGES DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT RD1/RDP1 RD2/RDP2 CV1/RDN1 CV2/RDN2 O34 26 33 27 RDn: Receive Data output for Channel 1~2 In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI, HDB3 or B8ZS line code rules. CVn: Code Violation indication In single rail mode, the BPV/CV errors in received data stream will be reported by driving the CVn pin to high level for a full clock cycle. B8ZS/HDB3 line code violation can be indicated if the B8ZS/HDB3 decoder is enabled. When AMI decoder is selected, bipolar violation will be indicated. In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CVn pin if single rail mode is chosen. RDPn/RDNn: Positive/Negative Receive Data output for Channel 1~2 In dual rail mode, these pins output the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data if CDR is bypassed. Active edge and level select: Data on RDPn/RDNn or RDn is clocked with either the rising or the falling edge of RCLKn. The active polarity is also select- able. Refer to RECEIVE PATH SYSTEM INTERFACE for details. RCLK1 RCLK2 O35 25 RCLKn: Receive Clock output for Channel 1~2 This pin outputs 1.544 MHz for T1/J1 mode or 2.048 MHz for E1 mode receive clock. Under LOS conditions with AIS enabled (bit AISE=1), RCLKn is derived from MCLK. In clock recovery mode, this signal provides the clock recovered from the RTIPn/RRINGn signal. The receive data (RDn in single rail mode or RDPn and RDNn in dual rail mode) is clocked out of the device on the active edge of RCLKn. If clock recovery is bypassed, RCLKn is the exclusive OR (XOR) output of the dual rail slicer data RDPn and RDNn. This signal can be used in applications with external clock recovery circuitry. MCLK I 30 MCLK: Master Clock input A built-in clock system that accepts selectable 2.048MHz reference for E1 operating mode and 1.544MHz reference for T1/ J1 operating mode. This reference clock is used to generate several internal reference signals: • Timing reference for the integrated clock recovery unit. • Timing reference for the integrated digital jitter attenuator. • Timing reference for microcontroller interface. • Generation of RCLKn signal during a loss of signal condition. • Reference clock to transmit All Ones, all zeros, PRBS/QRSS pattern as well as activate or deactivate Inband Loop- back code if MCLK is selected as the reference clock. Note that for ATAO and AIS, MCLK is always used as the refer- ence clock. • Reference clock during Transmit All Ones (TAO) condition or sending PRBS/QRSS in hardware control mode. The loss of MCLK will turn TTIP/TRING into high impedance status. LOS1 LOS2 O32 28 LOSn: Loss of Signal Output for Channel 1~2 These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received signal in channel n. The LOS pin will become low automatically when valid received signal is detected again. The criteria of loss of signal are described in 3.6 LOS AND AIS DETECTION. REF I 71 REF: reference resister An external resistor (3k Ω, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit. Table-1 Pin Description (Continued) Name Type Pin No. Description |
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