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EL7520ILZ Datasheet(PDF) 8 Page - Intersil Corporation |
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EL7520ILZ Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 18 page 8 FN7318.0 July 12, 2005 EL7520, EL7520A Pin Descriptions PIN NUMBER PIN NAME FUNCTION DESCRIPTION 1 CDLY With a capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault timeout time 2 DRVB Gate driver output for the external N channel switch; the pulse voltage follows the input voltage 3 PGND Power GND 4 ISAD With a resistor connected from this pin to GND sets the current limit of the external N channel FET 5 ISIN Sense the drain voltage of the external N channel FET and connected to the internal current limit comparator 6 DELB Active low control output for optional delay control for external VBOOST P channel FET; when fault is detected, this pin goes to high 7 SGND Low noise signal ground 8 FBB Boost regulator voltage feedback input pin; regulates to 1.2V nominal 9CINT VBOOST integrator output, connect 2.2nF to analog GND for PI mode or connect to VREF for P mode operation 10 VREF Bandgap voltage bypass terminal; bypass with a 0.1µF to analog GND; can be used as charge pump reference 11 FBN Negative LDO voltage feedback input pin; regulates to 0.2V nominal 12 DRVN Negative LDO base drive; open drain of an internal P channel MOSFET 13 FBL Logic LDO voltage feedback input pin; regulates to 1.2V nominal 14 DRVL Logic LDO base drive; open drain of an internal N channel MOSFET 15 FBP Positive LDO voltage feedback input pin; regulates to 1.2V nominal 16 DRVP Positive LDO base drive; open drain of an internal N channel MOSFET 17 EN Enable pin for the chip; high enable; low disabled 18 VDD Positive supply for all internal circuitry except DRVB 19 VDDP Positive supply for external N channel FET gate drive (DRVB) 20 PG Output gate drive of the external fault protection P channel FET; when chip is disabled or when a fault has been detected, this pin is high |
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