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M5M5V4R01J-15 Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor |
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M5M5V4R01J-15 Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor |
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2 / 6 page  M5M5V4R01J-12,-15 4194304-BIT (4194304-WORD BY 1-BIT) CMOS STATIC RAM MITSUBISHI ELECTRIC MITSUBISHI LSIs 2 The operation mode of the M5M5V4R01J is determined by a combination of the device control inputs S, W and OE. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level S. The address must be set-up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is excuted by setting W at a high level and OE at a low level while S are in an active state (S=L). When setting S at high level, the chip is in a non-selectable mode in which both reading and writing are disable. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by S. Signal-S controls the power-down feature. When S goes high, power dissapation is reduced extremely. The access time from S is equivalent to the address access time. The RAM works with an organization of 4194304-word by 1 bit,when B1/B4 is low of floating. And an organization of 10485 76-word by 4bit is also obtained for reducing the test time, when B1/B4 is high. FUNCTION Icc S W OE H Mode Non selection Stand by D High-impedance XX FUNCTION TABLE L Write Active Din L X L Read Active HL L Active High-impedance HH Q Dout High-impedance High-impedance High-impedance High-impedance ABSOLUTE MAXIMUM RATINGS Operating temperature V cc VI VO Pd Topr Tstg V V V mW -2.0 ~ 4.6 1000 0 ~ 70 Parameter Supply voltage Input voltage Output voltage Power dissipation Storage temperature (bias) Symbol Unit Conditions With respect to GND Ratings * Tstg(bias) Storage temperature -10 ~ 85 VIH VIL VOH V V V Vcc+0.3 0.8 2.2 2.0 VOL 0.4 Symbol Parameter Max Typ Limits Min Condition Unit High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage I I I CC1 I CC2 I CC3 mA mA 160 I OZ 2 10 AC DC 10 Input current Active supply current (TTL level) Stand by current (TTL level) Output current in off-state Stand by current 90 100 150 12ns cycle V 15ns cycle mA 75 AC DC 50 70 12ns cycle 15ns cycle 1 -2.0 ~ VCC+0.5 * -65 ~ 150 C C C Ta=25 C *Pulse width ≤ 20ns, In case of DC:-0.5V -0.3 µA µA IOH =-4mA IOL= 8mA V I = 0~Vcc VI (S)= VIL other inputs V IH or VIL Output-open(duty 100%) VI (S)= Vcc ≥0.2V other inputs VI ≤0.2V or VI ≥Vcc-0.2V VI (S)= VIH VI (S)= VIH VO= 0~Vcc -2.0 ~ VCC+0.5 * DC ELECTRICAL CHARACTERISTICS +10% -5% (Ta=0 ~ 70 C, Vcc=3.3V unless otherwise noted) |
Similar Part No. - M5M5V4R01J-15 |
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Similar Description - M5M5V4R01J-15 |
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