11

avoided because of their additional series inductance. Use

of sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance that can result in

compromised performance. Minimizing parasitic capacitance

at the amplifier’s inverting input pin is very important. The

feedback resistor should be placed very close to the

inverting input pin. Strip line design techniques are

recommended for the signal traces.

Typical Applications

VIDEO SYNC PULSE REMOVER

Many CMOS analog to digital converters have a parasitic

latch up problem when subjected to negative input voltage

levels. Since the sync tip contains no useful video

information and it is a negative going pulse, we can chop it

off. Figure 31 shows a gain of 2 connections for EL8302.

Figure 32 shows the complete input video signal applied at

the input, as well as the output signal with the negative going

sync pulse removed.

MULTIPLEXER

Besides the normal power down usage, the ENABLE pin of

the EL8302 can be used for multiplexing applications. Figure

33 shows two channels with the outputs tied together, driving

a back terminated 75

to Amp B. Figure 34 shows the ENABLE signal and the

before-make operation of the multiplexing. Amp A is on and

signal is low and turns off in about 25ns when the ENABLE

passed through to the output. The break-before-make

operation ensures that more than one amplifier isn’t trying to

drive the bus at the same time.

SINGLE SUPPLY VIDEO LINE DRIVER

The EL8302 is wideband rail-to-rail output op amplifiers with

large output current, excellent dG, dP, and low distortion that

allow them to drive video signals in low supply applications.

Figure 35 is the single supply non-inverting video line driver

configuration and Figure 36 is the inverting video ling driver

are used to level shift the input and output to provide the

to minimize the droop of the luminance signal.

FIGURE 31. SYNC PULSE REMOVER

5V

1K

75

Ω

+

-

75

Ω

1K

75

Ω

FIGURE 32. VIDEO SIGNAL

1V

0.5V

0V

1V

0.5V

0V

M = 10µs/DIV

FIGURE 33. TWO TO ONE MULTIPLEXER

+2.5V

1K

2MHz

75

Ω

+

-

1K

75

Ω

-2.5V

75

Ω

B

+2.5V

1K

2MHz

+

-

1K

75

Ω

-2.5V

A

ENABLE

FIGURE 34.

0V

-0.5V

-1.5V

-2.5V

1V

0V

M = 50ns/DIV

A

ENABLE

B

-1V

EL8302