8

FN7458.1

September 21, 2005

AC Test Circuits

Pin Descriptions

PIN NUMBER

PIN NAME

EQUIVALENT

CIRCUIT

DESCRIPTION

1

S0

Circuit 2

Channel selection pin LSB (binary logic code)

2

GND

Circuit 4

Ground pin

3

IN0

Circuit 1

Input for channel 0

4

ENABLE

Circuit 2

Device enable (active low); there are internal pull-down resistors, so the device will be active with

no connection; "HI" puts device into power-down mode

5

IN1

Circuit 1

Input for channel 1

6

HIZ

Circuit 2

Output disable (active high); there are internal pull-down resistors, so the device will be active with

no connection; “HI” puts the output in high impedance state

7

V-

Circuit 4

Negative power supply

8

V+

Circuit 4

Positive power supply

9

OUT

Circuit 3

Output

10

IN-

Circuit 1

Inverting input of output amplifier

FIGURE 24A. TEST CIRCUIT FOR MEASURING WITH A 50

Ω OR

75

Ω INPUT TERMINATED EQUIPMENT.

INPUT TERMINATED EQUIPMENT.

NOTE: Figure 24A illustrates the optimum output load when connecting to input terminated equipment. Figure 24B illustrates back loaded test circuit

for video cable applications.

IN

V+

V-

CIRCUIT 1.

LOGIC PIN

V+

V-

GND.

33K

21K

+

-

1.2V

CIRCUIT 2.

V+

V-

OUT

CIRCUIT 3.

V-

V+

CAPACITIVELY

COUPLED

ESD CLAMP

GND

CIRCUIT 4.

TEST EQUIPMENT

50

Ω

or

75

Ω

50

Ω

or

75

Ω

50

Ω

or

75

Ω

Av = 1, 2

475

Ω

or

462.5

Ω

ISL59421

TEST EQUIPMENT

50

Ω

or

75

Ω

50

Ω

or

75

Ω

50

Ω

or

75

Ω

Av = 1, 2

475

Ω

or

462.5

Ω

ISL59421

ISL59421