MITSUBISHI ELECTRIC

M5M5V216AWG

revision-01, ' 98.12.08

2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI LSIs

6

Note 3: Hatching indicates the state is "don't care".

Note 4: A Write occurs during S low , overlaps BC1 and/or BC2 low and W low.

Note 6: Don't apply inverted phase signal externally when DQ pin is in output mode.

Note 5: When the falling edge of W is simultaneously or priorto the falling edge of BC1 and/or BC2 or the falling edge of S,

W

Write cycle (BC control mode)

DATA IN

STABLE

(Note3)

(Note3)

(Note4)

(Note5)

W

S

Write cycle (S control mode)

DATA IN

STABLE

(Note3)

(Note3)

(Note4)

(Note5)

(Note3)

(Note3)

S

BC1

BC2

and / or

(Note3)

(Note3)

(Note4)

BC1

BC2

and / or

the outputs are maintained in the high impedance state.