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M5M5V4R08J-12 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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M5M5V4R08J-12 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
1 / 12 page M5M5V4R08J-12,-15,-20 MITSUBISHI LSIs 4194304-BIT (524288-WORD BY 8-BIT) CMOS STATIC RAM MITSUBISHI ELECTRIC 1 Outline 36P0K (SOJ) PRELIMINARY data inputs/ outputs data inputs/ outputs data inputs/ outputs data inputs/ outputs write control input chip select input output enable input PIN CONFIGURATION (TOP VIEW) Notice: This is not a final specification. Some parametric limits are subject to change 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A3 A2 A1 A0 DQ1 36 35 34 33 32 31 30 29 28 27 26 25 24 23 OE S DQ5 DQ7 DQ6 A4 W A9 A8 A7 A6 A5 DQ2 DQ3 DQ4 DQ8 22 21 GND GND 1997.02.06 Rev.D DESCRIPTION The M5M5V4R08J is a family of 524288-word by 8-bit static RAMs, fabricated with the high performance CMOS silicon gate process and designed for high speed application. The M5M5V4R08J is offered in a 36-pin plastic small outline J-lead package(SOJ). These device operate on a single 3.3V supply, and are directly TTL compatible. They include a power down feature as well. APPLICATION High-speed memory units FEATURES address inputs address inputs address inputs address inputs VCC VCC (0V) (0V) (3.3V) (3.3V) COLUMN ADDRESS DECODERS A16 A15 A14 A13 A12 A11 A10 A9 20 21 22 23 24 18 32 33 A5 A8 A7 A6 A4 A3 A2 A1 A0 1 2 3 4 5 14 15 16 17 S 6 OE 31 W 13 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 7 8 11 12 25 26 29 30 COLUMN I/O CIRCUITS COLUMN INPUT BUFFERS VCC 27 GND 10 9 28 MEMORY ARRAY 512 ROWS 8192 COLUMNS COLUMN ADDRESS DECODERS (3.3V) (0V) BLOCK DIAGRAM address inputs address inputs data inputs/ outputs PACKAGE 36pin 400mil SOJ 17 18 A18 NC A17 A16 A15 A12 A10 A11 A14 A13 20 19 NC A17 A16 34 35 • Fast access time M5M5V4R08J-12 •••• 12ns(max) M5M5V4R08J-15 •••• 15ns(max) M5M5V4R08J-20 •••• 20ns(max) • Low power dissipation Active •••••••••• 363mW(typ) Stand by ••••••• 3.3mW(typ) • Single +3.3V power supply • Fully static operation : No clocks, No refresh • Common data I/O • Easy memory expansion by S • Three-state outputs : OR-tie capability • OE prevents data contention in the I/O bus • Directly TTL compatible : All inputs and outputs |
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