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HDMP-2689 Datasheet(PDF) 7 Page - Agilent(Hewlett-Packard) |
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HDMP-2689 Datasheet(HTML) 7 Page - Agilent(Hewlett-Packard) |
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7 / 28 page  7 Reset is initiated externally with the assertion of the RSTN pin. Before asserting the RSTN pin, the power supply to the chip and the reference clock (RFCP/N) must be stable for at least 20 µs. The RSTN pin must be held low for at least 100 ns. After reset is de-asserted, 500 µs must elapse before initiat- ing MDIO transactions (see Figure 13). Note that the transmit byte clocks (TCn) should be running and stable when reset is released to minimize the variation in transmit latency. Power Management The HDMP-2689 incorporates the ability to power down any channel which is unused. Both the channel and the associated output driver should be disabled by programming the unused channel’s register 24, bit 0 and register 26, bit 7 both to logic 0. Additionally, the HDMP-2689 does not require a particular power turn-on sequence. Power Supply Decoupling Recommended power supply filtering and placement of decoupling capacitors for the HDMP-2689 are shown in Figure 22 and Figure 23. Test The HDMP-2689 has several features to facilitate testing, including boundary scan, SerDes self-test, and loopback for link debugging. Boundary scan is implemented according to the IEEE 1149.1 standard. The instructions listed in Table 7 are supported. The HDMP-2689 also provides self-test capabilities with user-entered patterns or on- chip generation of pseudo- random bit streams (PRBS 27– 1). The patterns can be looped back either internally or externally from the transmit serializer to the receive deserializer and are verified within the chip. These self-test mechanisms are initi- ated and the error status re- ported through the MII manage- ment interface. To run a self-test, first select the pattern or set of patterns, then configure the loopback and check the results. Once enabled, the test pattern is sent continuously. To select a user-defined pattern: • Disable comma alignment by programming bit 1 of register 24 to logic 0. • Program the pattern (any pattern except all 0’s or all 1’s) into bits 9 through 0 of register 25. • To alternate the user pattern with its inverse, program bit 11 of register 25 to logic 1. • Program bit 10 of register 25 to a logic 1 to enable the user register pattern to be sent. To select PRBS data: • Disable comma alignment by programming bit 1 of register 24 to logic 0. • Program a non-zero seed for the pattern generator into bits 9 through 0 of register 25. • To send the PRBS pattern inverted, program bit 11 of register 25 to logic 1. • Program bit 12 of register 25 to a logic one to enable the PRBS pattern to be sent. • To see the recovered PRBS data on the parallel interface, comma edge alignment should be disabled by programming bit 13 of register 17 to logic 0. To run the self-test with either external or internal loopback: • Set up either a user-defined pattern or PRBS data as outlined above. • To run with internal loopback, program bit 13 of register 25 to logic 1. • To run with external loopback, connect the high-speed output of the channel being tested (TXAP/N, TXBP/N, TXCP/N, TXDP/N) back to its high speed input (RXAP/N, RXBP/N, RXCP/N, RXDP/N). Bit 13 of register 25 must be logic 0 (default value after reset). • Program bit 14 of register 25 to logic 0 if it is not already zero (default value after a reset). Bit 12 of register 27 (pattern failure detect) and bit 11 of register 27 (test run complete) should both now be logic 0. • Program bit 14 of register 25 (pattern error monitor enable) to logic 1. This starts the pattern checking process. For a PRBS pattern 2 9 bytes are checked before the test is considered complete. • Monitor bit 11 of register 27 to determine if a sufficient number of cycles have elapsed for test completion. When this bit is logic 1, bit 12 of register 27 signals pass (logic 0) or fail (logic 1). To allow link debugging: • Configure the HDMP-2689 for internal loopback (data pro- vided at the parallel input is looped back to the parallel output after traversing the chip) via management interface register 25 bit 13. Note that for internal loopback in codec mode the receiver sees a loss of signal and error bit 9 (see Table 2) is set, unless the high speed inputs (ignored for internal loopback) are being driven. |
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Similar Description - HDMP-2689 |
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