IDT70V9179L9PFI datasheet(3/15 Pages) IDT

Part #	IDT70V9179L9PFI

Description	HIGH-SPEED 3.3V 32K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM

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Manufacturer	IDT [Integrated Device Technology]

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3 / 15 page

6.42

IDT70V9179L

High-Speed 3.3V 32K x 9 Dual-Port Synchronous Pipelined Static RAM

Industrial and Commercial Temperature Ranges

3

Preliminary

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2.

ADS, CNTEN, CNTRST = X.

3.

OE is an asynchronous input signal.

Truth Table IRead/Write and Enable Control(1,2,3)

Pin Names

Left Port

Right Port

Names

CE0L, CE1L

CE0R, CE1R

Chip Enables

R/

WL

R/

WR

Read/Write Enable

OEL

OER

Output Enable

A0L - A14L

A0R - A14R

Address

I/O0L - I/O8L

I/O0R - I/O8R

Data Input/Output

CLKL

CLKR

Clock

ADSL

ADSR

Address Strobe Enable

CNTENL

CNTENR

Counter Enable

CNTRSTL

CNTRSTR

Counter Reset

FT/PIPEL

FT/PIPER

Flow-Through / Pipeline

VDD

Power (3.3V)

VSS

Ground (0V)

5645 tbl 01

OE

CLK

CE0

CE1

R/

W

I/O0-8

MODE

X

↑

H

X

High-Z

Deselected–Power Down

X

↑

X

L

X

High-Z

Deselected–Power Down

X

↑

LH

L

DATAIN

Write

L

↑

LH

H

DATAOUT

Read

H

X

L

H

X

High-Z

Outputs Disabled

5645 tbl 02

Truth Table IIAddress Counter Control(1,2,6)

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2.

CE0 and OE = VIL; CE1 and R/W = VIH.

3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.

4.

ADS and CNTRST are independent of all other signals including CE0 and CE1.

5. The address counter advances if

CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.

6. While an external address is being loaded (

ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.

Address

Addr

Used

CLK(6)

ADS

CNTEN

CNTRST

I/O(3)

MODE

An

X

An

↑

L(4)

XH

DI/O (n)

External Address Used

XAn

An + 1

↑

H

L(5)

HDI/O(n+1)

Counter Enabled—Internal Address generation

X

An + 1

↑

HH

H

DI/O(n+1)

External Addre ss Blocked—Counter disabled (An + 1 reused)

XX

Ao

↑

XX

L(4)

DI/O(0)

Counter Reset to Address 0

5645 tbl 03

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