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IDT70V9179L12PFI Datasheet(PDF) 9 Page - Integrated Device Technology |
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IDT70V9179L12PFI Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 15 page 6.42 IDT70V9179L High-Speed 3.3V 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges 9 Preliminary Timing Waveform with Port-to-Port .low-Through Read(4,5,7) Timing Waveform of a Bank Select Pipelined Read(1,2) tSC tHC CE0(B1) ADDRESS(B1) A0 A1 A2 A3 A4 A5 tSA tHA CLK 5645 drw 08 Q0 Q1 Q3 DATAOUT(B1) tCH2 tCL2 tCYC2 (3) ADDRESS(B2) A0 A1 A2 A3 A4 A5 tSA tHA CE0(B2) DATAOUT(B2) Q2 Q4 tCD2 tCD2 tCKHZ tCD2 tCKLZ tDC tCKHZ tCD2 tCKLZ (3) (3) tSC tHC (3) tCKHZ (3) tCKLZ (3) tCD2 A6 A6 tDC tSC tHC tSC tHC DATAIN "A" CLK "B" R/ W "B" ADDRESS "A" R/ W "A" CLK "A" ADDRESS "B" NO MATCH MATCH NO MATCH MATCH VALID tCWDD tCD1 tDC DATAOUT "B" 5645 drw 09 VALID VALID tSW tHW tSA tHA tSD tHD tHW tCD1 tCCS tDC tSA tSW tHA (6) (6) NOTES: 1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9179 for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH. 3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). 4. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. 5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case. 7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A". |
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