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IDT5991A-5JI Datasheet(PDF) 2 Page - Integrated Device Technology |
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IDT5991A-5JI Datasheet(HTML) 2 Page - Integrated Device Technology |
2 / 8 page 2 COMMERCIALANDINDUSTRIALTEMPERATURERANGES IDT5991A PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK PIN CONFIGURATION NOTE: 1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability. ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit Supply Voltage to Ground –0.5 to +7 V VI DC Input Voltage –0.5 to +7 V TJ Junction Temperature 150 °C TSTG Storage Temperature –65 to +150 °C NOTE: 1. Capacitance applies to all inputs except TEST, FS, and nF1:0. CAPACITANCE(TA=+25°C,f=1MHz,VIN=0V) Parameter Description Typ. Max. Unit CIN InputCapacitance 5 7 pF PIN DESCRIPTION Pin Name Type Description REF IN ReferenceClockInput FB IN FeedbackInput TEST(1) IN When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections (see Control SummaryTable)remainineffect. SetLOWfornormaloperation. GND/ sOE (1) IN Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0 and 3Q1may be used as thefeedbacksignaltomaintainphaselock. WhenTESTisheldatMIDlevelandGND/sOEisHIGH,thenF[1:0]pinsactasoutputdisable controls for individual banks when nF[1:0] = LL. Set GND/sOE LOW for normal operation. VCCQ/PE IN Selectablepositiveornegativeedgecontrol. WhenLOW/HIGHtheoutputsaresynchronizedwiththenegative/positiveedge ofthe referenceclock. nF[1:0] IN 3-level inputs for selecting 1 of 9 skew taps or frequency functions FS IN Selectsappropriateoscillatorcircuitbasedonanticipatedfrequencyrange. (SeePLLProgrammableSkewRange.) nQ[1:0] OUT Fourbanksoftwooutputswithprogrammableskew VCCN PWR Powersupplyforoutputbuffers VCCQ PWR Powersupplyforphase lockedloop and other internal circuitry GND PWR Ground NOTE: 1.When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. PLCC TOP VIEW Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked compo- nents. Skew is selectable as a multiple of a time unit tU which is of the order of a nanosecond (see PLL Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the nF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the nF1:0 control pins. PROGRAMMABLESKEW 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 3F1 4F0 4F1 VCCQ/PE 4Q1 4Q0 GND GND 2F0 GND/sOE 1F1 1F0 1Q0 1Q1 GND GND 4 3 2 1 32 31 30 14 15 16 17 18 19 20 VCCN VCCN |
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