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ST7DALI Datasheet(PDF) 56 Page - STMicroelectronics |
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ST7DALI Datasheet(HTML) 56 Page - STMicroelectronics |
56 / 141 page ST7DALI 56/141 12-BIT AUTORELOAD TIMER (Cont’d) 11.2.3 Functional Description PWM Mode This mode allows up to four Pulse Width Modulat- ed signals to be generated on the PWMx output pins. The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR regis- ter. PWM Frequency and Duty Cycle The four PWM signals have the same frequency (fPWM) which is controlled by the counter period and the ATR register value. fPWM = fCOUNTER / (4096 - ATR) Following the above formula, – If fCOUNTER is 32 MHz, the maximum value of fPWM is 8 MHz (ATR register value = 4092), the minimum value is 8 KHz (ATR register value = 0) – If fCOUNTER is 4 Mhz, the maximum value of fPWM is 2 MHz (ATR register value = 4094),the mini- mum value is 1 KHz (ATR register value = 0). Note: The maximum value of ATR is 4094 be- cause it must be lower than the DCR value which must be 4095 in this case. At reset, the counter starts counting from 0. When a upcounter overflow occurs (OVF event), the preloaded Duty cycle values are transferred to the Duty Cycle registers and the PWMx signals are set to a high level. When the upcounter match- es the DCRx value the PWMx signals are set to a low level. To obtain a signal on a PWMx pin, the contents of the corresponding DCRx register must be greater than the contents of the ATR register. The polarity bits can be used to invert any of the four output signals. The inversion is synchronized with the counter overflow if the TRAN bit in the TRANCR register is set (reset value). See Figure 34. Figure 34. PWM Inversion Diagram The maximum available resolution for the PWMx duty cycle is: Resolution = 1 / (4096 - ATR) Note: To get the maximum resolution (1/4096), the ATR register must be 0. With this maximum reso- lution, 0% and 100% can be obtained by changing the polarity. Figure 35. PWM Function PWMx PWMx PIN counter overflow OPx PWMxCSR Register inverter DFF TRAN TRANCR Register DUTY CYCLE REGISTER AUTO-RELOAD REGISTER t 4095 000 WITH OE=1 AND OPx=0 (ATR) (DCRx) WITH OE=1 AND OPx=1 1 |
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