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ST7DALI Datasheet(PDF) 92 Page - STMicroelectronics

Part No. ST7DALI
Description  8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY, DATA EEPROM, ADC, TIMERS, SPI, DALI
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Maker  STMICROELECTRONICS [STMicroelectronics]
Homepage  http://www.st.com
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ST7DALI
92/141
10-BIT A/D CONVERTER (ADC) (Cont’d)
11.6.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bit 4:3 = Reserved. Must be kept cleared.
Bit 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
Bit 7:0 = D[9:2] MSB of Analog Converted Value
AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
Read/Write
Reset Value: 0000 00xx (0xh)
Bit 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software. User is sug-
gested to use this bit to calibrate the ADC when
amplifier is ON. Setting this bit internally connects
amplifier input to 0v. Hence, corresponding ADC
output can be used in software to eliminate ampli-
fier-offset error.
0: Calibration off
1: Calibration on. (The input voltage of the amp is
set to 0V)
Note: It is advised to use this bit to calibrate the
ADC when the amplifier is ON. Setting this bit in-
ternally connects the amplifier input to 0v. Hence,
the corresponding ADC output can be used in soft-
ware to eliminate an amplifier-offset error.
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
70
EOC
SPEED ADON
0
CH3
CH2
CH1
CH0
Channel Pin*
CH2
CH1
CH0
AIN0
0
0
0
AIN1
0
0
1
AIN2
0
1
0
AIN3
0
1
1
AIN4
1
0
0
AIN5
1
0
1
AIN6
1
1
0
70
D9
D8
D7
D6
D5
D4
D3
D2
70
00
0
AMP
CAL
SLOW
AMP-
SEL
D1
D0
fADC
SLOW SPEED
fCPU/2
00
fCPU
01
fCPU/4
1x
1




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