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M5M5V416BTP-70LW Datasheet(PDF) 4 Page - Mitsubishi Electric Semiconductor |
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M5M5V416BTP-70LW Datasheet(HTML) 4 Page - Mitsubishi Electric Semiconductor |
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4 / 11 page  M ITSUBISHI ELECTRIC M5M5V416BTP,RT revision-P04, ' 98.12.16 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change AC ELECTRICAL CHARACTERISTICS (Vcc=2.7 ~ 3.6V, unless otherwise noted) Input rise time and f all time Ref erence lev el Output loads 2.7V~3.6V VIH=2.4V,VIL=0.4V VOH=VOL=1.5V Transition is measured ±500mV f rom steady state voltage.(f or ten,t dis) 5ns Fig.1,CL=30pF CL=5pF (for ten,tdis) (1) TEST CONDITIONS Supply v oltage Input pulse 1TTL CL DQ Fig.1 Output load Including scope and jig capacitance tCR ns ta(S1) ta(OE) tdis(S1) tdis(OE) ten(S1) ten(OE) tV(A) ta(A) 10 70L,70H,70LW 70HW,70LI,70HI 45 ns ns ns ns ns ns ns ns ta(BC1) ta(BC2) tdis(BC1) tdis(BC2) ten(BC1) ten(BC2) ns ns ns ns ns ns 85 85 85 85 30 30 30 30 10 10 5 10 100 10 50 100 100 100 100 35 35 35 35 10 10 5 10 ta(S2) ns 85 100 ten(S2) 10 ns 10 tdis(S2) ns 30 35 70 85 10 10 10 10 10 35 70 70 70 70 25 25 25 25 70 25 85L,85H,85LW 85HW,85LI,85HI 10L,10H,10LW 10HW,10LI,10HI 4 tsu(A-WH) tCW tw(W) tsu(A) tsu(S1) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) ns 70 ns ns ns ns ns ns ns ns ns ns ns ns ns 55 0 65 25 25 5 5 tsu(BC1) tsu(BC2) 65 65 65 35 0 0 35 35 tsu(S2) ns 65 70L,70H,70LW 70HW,70LI,70HI 85L,85H,85LW 85HW,85LI,85HI 10L,10H,10LW 10HW,10LI,10HI 30 30 100 75 0 85 5 5 85 85 85 40 0 0 85 85 60 0 70 5 5 70 70 70 35 0 0 70 Symbol Parameter Read cy cle time Limits Address access time Chip select 1 access time Chip select 2 access time By te control 1 access time By te control 2 access time Output enable access time Output disable time aft er S2 low Output disable time aft er S1 high Output disable time aft er BC1 high Max Min Max Min Max Min Units (2) READ CYCLE Output disable time aft er BC2 high Output disable time aft er OE high Output enable time af ter S1 low Output enable time af ter S2 high Output enable time af ter BC1 low Output enable time af ter BC2 low Output enable time af ter OE low Data v alid time after address (3) WRITE CYCLE Max Min Max Min Max Min Limits Units Write cy cle time Write pulse width Address setup time By te control 1 setup time By te control 2 setup time Chip select 1 setup time Chip select 2 setup time Data setup time Data hold time Write recov ery time Output disable time f rom W low Output disable time f rom OE high Output enable time f rom W high Output enable time f rom OE low Symbol Parameter Address setup time with respect to W |
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