MC74HC174AN datasheet(1/8 Pages) ONSEMI

Part #	MC74HC174AN

Description	Hex D Flip-Flop with Common Clock and Reset

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March, 2000 – Rev. 7

1

Publication Order Number:

MC74HC174A/D

MC74HC174A

Hex D Flip-Flop with

Common Clock and Reset

High–Performance Silicon–Gate CMOS

The MC74HC174A is identical in pinout to the LS174. The device

inputs are compatible with standard CMOS outputs; with pullup

resistors, they are compatible with LSTTL outputs.

This device consists of six D flip–flops with common Clock and

Reset inputs. Each flip–flop is loaded with a low–to–high transition of

the Clock input. Reset is asynchronous and active–low.

• Output Drive Capability: 10 LSTTL Loads

• TTL NMOS Compatible Input Levels

• Outputs Directly Interface to CMOS, NMOS, and TTL

• Operating Voltage Range: 4.5 to 5.5 V

• Low Input Current: 1.0 µA

• In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

• Chip Complexity: 162 FETs or 40.5 Equivalent Gates

LOGIC DIAGRAM

PIN 16 = VCC

PIN 8 = GND

3

4

6

11

13

14

2

5

7

10

12

15

D0

D1

D2

D3

D4

D5

Q0

Q1

Q2

Q3

Q4

Q5

CLOCK

9

RESET 1

DATA

INPUTS

NONINVERTING

OUTPUTS

FUNCTION TABLE

Inputs

Output

Reset

Clock

D

Q

LX

X

L

HH

H

HL

L

H

L

X

No Change

H

X

No Change

Design Criteria

Value

Units

Internal Gate Count*

40.5

ea.

Internal Gate Propagation Delay

1.5

ns

Internal Gate Power Dissipation

5.0

µW

Speed Power Product

.0075

pJ

*Equivalent to a two–input NAND gate.

SO–16

D SUFFIX

CASE 751B

http://onsemi.com

1

16

PDIP–16

N SUFFIX

CASE 648

1

16

MARKING

DIAGRAMS

1

16

MC74HC174AN

AWLYYWW

1

16

HC174A

AWLYWW

A

= Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

Device

Package

Shipping

ORDERING INFORMATION

MC74HC174AN

PDIP–16

2000 / Box

MC74HC174AD

SOIC–16

48 / Rail

MC74HC174ADR2

SOIC–16

2500 / Reel

PIN ASSIGNMENT

13

14

15

16

9

10

11

12

5

4

3

2

1

8

7

6

Q4

D4

D5

Q5

VCC

CLOCK

Q3

D3

D1

D0

Q0

RESET

GND

Q2

D2

Q1

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