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ISL8010IUZ-T13 Datasheet(PDF) 11 Page - Intersil Corporation |
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ISL8010IUZ-T13 Datasheet(HTML) 11 Page - Intersil Corporation |
11 / 12 page 11 FN6191.0 September 27, 2005 Thermal Performance The ISL8010 is available in a fused-lead MSOP10. Compared with regular MSOP10 package, the fused-lead package provides lower thermal resistance. The θJA is 100°C/W on a 4-layer board and 125°C/W on 2-layer board. Maximizing the copper area around the pins will further improve the thermal performance. Output Voltage Selection Users can set the output voltage of the variable version with a resister divider, which can be chosen based on the following formula: Component Selection Because of the fixed internal compensation, the component choice is relatively narrow. For a regulator with fixed output voltage, only two capacitors and one inductor are required. It is recommended to use between 10µF and 22µF multilayer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and 1.5µH to 2.2µH for the inductor. The RMS current present at the input capacitor is decided by the following formula: This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. The inductor peak-to-peak ripple current is given as: L is the inductance fS the switching frequency (nominally 1.4MHz) The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 2A surge current that can occur during a current limit condition. Layout Considerations The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: 1. Separate the Power Ground ( ) and Signal Ground ( ); connect them only at one point right at the pins 2. Place the input capacitor as close to VIN and PGND pins as possible 3. Make the following PC traces as small as possible: 4. from LX pin to L 5. from CO to PGND 6. If used, connect the trace from the FB pin to R1 and R2 as close as possible 7. Maximize the copper area around the PGND pin 8. Place several via holes under the chip to additional ground plane to improve heat dissipation The demo board is a good example of layout based on this outline. Please refer to the ISL8010 Application Brief. VO 0.8 1 R2 R1 ------- + × = IINRMS VO VIN VO – () × VIN ----------------------------------------------- IO × = ∆I IL VIN ( VO) VO × – LVIN fS × × -------------------------------------------- = ISL8010 |
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