HD6432351 datasheet(10/989 Pages) RENESAS

Part #	HD6432351

Description	The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

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iv

6.2.5

Bus Control Register L (BCRL) ........................................................................... 132

6.2.6

Memory Control Register (MCR) ........................................................................ 134

6.2.7

DRAM Control Register (DRAMCR).................................................................. 137

6.2.8

Refresh Timer/Counter (RTCNT) ........................................................................ 140

6.2.9

Refresh Time Constant Register (RTCOR) .......................................................... 140

6.3

Overview of Bus Control ................................................................................................... 141

6.3.1

Area Partitioning................................................................................................... 141

6.3.2

Bus Specifications ................................................................................................ 142

6.3.3

Memory Interfaces................................................................................................ 143

6.3.4

Advanced Mode.................................................................................................... 144

6.3.5

Areas in Normal Mode.......................................................................................... 145

6.3.6

Chip Select Signals ............................................................................................... 146

6.4

Basic Bus Interface ............................................................................................................ 147

6.4.1

Overview............................................................................................................... 147

6.4.2

Data Size and Data Alignment.............................................................................. 147

6.4.3

Valid Strobes........................................................................................................ 149

6.4.4

Basic Timing......................................................................................................... 150

6.4.5

Wait Control.......................................................................................................... 158

6.5

DRAM Interface ................................................................................................................ 160

6.5.1

Overview............................................................................................................... 160

6.5.2

Setting DRAM Space............................................................................................ 160

6.5.3

Address Multiplexing............................................................................................ 160

6.5.4

Data Bus................................................................................................................ 161

6.5.5

Pins Used for DRAM Interface ............................................................................ 161

6.5.6

Basic Timing......................................................................................................... 162

6.5.7

Precharge State Control ........................................................................................ 163

6.5.8

Wait Control ......................................................................................................... 164

6.5.9

Byte Access Control ............................................................................................. 166

6.5.10 Burst Operation..................................................................................................... 168

6.5.11 Refresh Control..................................................................................................... 171

6.6

DMAC Single Address Mode and DRAM Interface ......................................................... 174

6.6.1

When DDS = 1...................................................................................................... 174

6.6.2

When DDS = 0...................................................................................................... 175

6.7

Burst ROM Interface.......................................................................................................... 176

6.7.1

Overview............................................................................................................... 176

6.7.2

Basic Timing......................................................................................................... 176

6.7.3

Wait Control.......................................................................................................... 178

6.8

Idle Cycle ........................................................................................................................... 179

6.8.1

Operation .............................................................................................................. 179

6.8.2

Pin States in Idle Cycle ......................................................................................... 183

6.9

Write Data Buffer Function ............................................................................................... 184

6.10

Bus Release........................................................................................................................ 185

6.10.1 Overview............................................................................................................... 185

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