M ITSUBISHI ELECTRIC

M5M5V416BWG

revision-W03, ' 98.12.16

4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI LSIs

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change

6

Note 3: Hatching indicates the state is "don't care".

Note 4: A Write occurs during S1 low, S2 high ov erlaps BC1 and/or BC2 low and W low.

Note 6: Don't apply inv erted phase signal externally when DQ pin is in output mode.

Note 5: When the f alling edge of W is simultaneously or prior to the f alling edge of BC1 and/or BC2 or the f alling edge of S1

W

Write cycle (BC control mode)

DATA IN

STABLE

(Note3)

(Note3)

(Note4)

(Note5)

(Note3)

(Note3)

S1

or rising edge of S2, the outputs are maintained in the high impedance state.

BC1 ,BC2

(Note3)

(Note3)

S2