MC74HC390A

http://onsemi.com

3

Unit

Guaranteed Limit

VCC

V

Test Conditions

Parameter

Symbol

Unit

v 125_C

v 85_C

– 55 to

25

_C

VCC

V

Test Conditions

Parameter

Symbol

Iin

Maximum Input Leakage

Current

Vin = VCC or GND

6.0

± 0.1

± 1.0

± 1.0

µA

ICC

Maximum Quiescent Supply

Current (per Package)

Vin = VCC or GND

Iout = 0 µA

6.0

4

40

160

µA

NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book

(DL129/D).

Guaranteed Limit

Symbol

Parameter

VCC

V

– 55 to

25

_C

v 85_C

v 125_C

Unit

fmax

Maximum Clock Frequency (50% Duty Cycle)

(Figures 1 and 3)

2.0

3.0

4.5

6.0

10

15

30

50

9

14

28

45

8

12

25

40

MHz

tPLH,

tPHL

Maximum Propagation Delay, Clock A to QA

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70

40

24

20

80

45

30

26

90

50

36

31

ns

tPLH,

tPHL

Maximum Propagation Delay, Clock A to QC

(QA connected to Clock B)

(Figures 1 and 3)

2.0

3.0

4.5

6.0

200

160

58

49

250

185

65

62

300

210

70

68

ns

tPLH,

tPHL

Maximum Propagation Delay, Clock B to QB

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70

40

26

22

80

45

33

28

90

50

39

33

ns

tPLH,

tPHL

Maximum Propagation Delay, Clock B to QC

(Figures 1 and 3)

2.0

3.0

4.5

6.0

90

56

37

31

105

70

46

39

180

100

56

48

ns

tPLH,

tPHL

Maximum Propagation Delay, Clock B to QD

(Figures 1 and 3)

2.0

3.0

4.5

6.0

70

40

26

22

80

45

33

28

90

50

39

33

ns

tPHL

Maximum Propagation Delay, Reset to any Q

(Figures 2 and 3)

2.0

3.0

4.5

6.0

80

48

30

26

95

65

38

33

110

75

44

39

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

2.0

3.0

4.5

6.0

75

27

15

13

95

32

19

15

110

36

22

19

ns

Cin

Maximum Input Capacitance

—

10

10

10

pF

1. For propagation delays with loads other than 50 pF, see Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25

°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Counter)*

35

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).