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AS7C33256PFS32A-133TQCN Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS7C33256PFS32A-133TQCN Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 20 page  November 2004 ® AS7C33256PFS32A AS7C33256PFS36A 3.3V 256K × 32/36 pipelined burst synchronous SRAM 11/30/04, v.3.1 Alliance Semiconductor P. 1 of 20 Copyright ©Alliance Semiconductor. All rights reserved. Features • Organization: 262,144 words x 32 or 36 bits • Fast clock speeds to 166 MHz • Fast clock to data access: 3.5/4.0 ns •Fast OE access time: 3.5/4.0 ns • Fully synchronous register-to-register operation • Single-cycle deselect • Asynchronous output enable control • Available in100-pin TQFP • Individual byte write and global write Logic block diagram Q0 Q1 256K × 32/36 Memory array Burst logic CLK CLR CE Address DQ CE CLK DQd CLK DQ Byte write registers register DQc CLK DQ Byte write registers DQb CLK DQ Byte write registers DQa CLK DQ Byte write registers Enable CLK DQ register Enable CLK DQ delay register CE Output registers Input registers Power down 4 36/32 18 16 18 18 GWE BWE BWd ADV ADSC ADSP CLK CE0 CE1 CE2 BWc BWb BWa OE A[17:0] ZZ LBO OE CLK CLK 36/32 36/32 DQ[a:d] 2 2 Selection guide –166 –133 Units Minimum cycle time 6 7.5 ns Maximum clock frequency 166 133 MHz Maximum clock access time 3.5 4 ns Maximum operating current 475 425 mA Maximum standby current 130 100 mA Maximum CMOS standby current (DC) 30 30 mA • Multiple chip enables for easy expansion • 3.3V core power supply • 2.5V or 3.3V I/O operation with separate VDDQ • Linear or interleaved burst control • Snooze mode for reduced power-standby • Common data inputs and data outputs • 30 mW typical standby power in power down mode |
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