128Mb: x4, x8, x16
DDR SDRAM
PDF: 09005aef80505d1b / Source: 09005aef80469e44
128Mb: x4, x8, x16 DDR SDRAM
Rev: 11/23/2004
10
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specifications without notice.
© 2001, 2002, 2004 SpecTek
NOTES, continued
22. MIN (
tRC or tRFC) for IDD measurements is the
smallest multiple of
tCK that meets the minimum
absolute value for the respective parameter.
tRAS
(MAX) for IDD measurements is the largest
multiple of
tCK that meets the maximum absolute
value for
tRAS.
23. The refresh period 64ms. This equates to an
average refresh rate of 15.625μs. However, an
AUTO REFRESH command must be asserted at
least once every 140.6μs; burst refreshing or
posting by the DRAM controller greater than
eight refresh cycles is not allowed.
24. The I/O capacitance per DQS and DQ byte/group
will not differ by more than this maxi-or mum
amount for any given device.
25. The valid data window is derived by achieving
other specifications -
tHP ( tCK/2), tDQSQ, and
tQH ( tQH = tHP - tQHS). The data valid window
derates directly proportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data
valid window derating curves are provided below
for duty cycles ranging between 50/50 and 45/55.
26. Referenced to each output group: x4 = DQS with
DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 =
LDQS with DQ0-DQ7 and UDQS with DQ8-
DQ15.
27. This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (
tRFC [MIN]) else
CKE is LOW (i.e., during standby).
28. To maintain a valid level, the transitioning edge of
the input must:
a) Sustain a constant slew rate from the Current
AC level through to the target AC level,
VIL(AC) VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue
to maintain at least the target DC level,
VIL(DC) or VIH(DC).
29. The Input capacitance per pin group will not differ
by more than this maximum amount for any given
device.
30. CK and CK# input slew rate must be >1V/ns.
31. DQ and DM input slew rates must not deviate from
DQS by more than 10%. If the DQ/DM/DQS slew rate
is less than 0.5V/ns, timing must be derated: 50ps
must be added to
tDS and tDH for each 100mv/ns
reduction in slew rate. If slew rate exceeds 4V/ns,
functionality is uncertain.
32. VDD must not vary more than 4% if CKE is not active
while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each timing
parameter is allowed to vary by the same amount.
34.
tHP min is the lesser of tCL minimum and tCH
minimum actually applied to the device CK and CK/
inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are
not allowed to be issued until
tRAS (MIN) can
be satisfied prior to the internal precharge
command being issued.
36. Applies to x16 only. First DQS (LDQS or UDQS) to
transition to last DQ (DQ0-DQ15) to transition valid.
Initial JEDEC specifications suggested this to be same
as
tDQSQ.
37. Note 37 is not used.
38. Note 38 is not used.
39. Note 39 is not used.
40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse
width < 3ns and the pulse width can not be greater
than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) =
-1.5V for a pulse width < 3ns and the pulse width can
not be greater than 1/3 of the cycle rate.
41. VDD and VDDQ must track each other.
42. Note 42 is not used.
43. Note 43 is not used.
44. During initialization, VddQ, Vtt, and Vref
must be equal to or less than Vdd + 0.3V.
Alternatively, Vtt may be 1.35V maximum
during power up, even if Vdd /VddQ are 0
volts, provided a minimum of 42 ohms of
series resistance is used between the Vtt
supply and the input pin.
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