HX6228

6

TAVAVR

Address Read Cycle Time

16

25

ns

TAVQV

Address Access Time

15

25

ns

TAXQX

Address Change to Output Invalid Time

12

3

ns

TSLQV

Chip Select Access Time

16

25

ns

TSLQX

Chip Select Output Enable Time

12

5

ns

TSHQZ

Chip Select Output Disable Time

5

10

ns

TEHQV

Chip Enable Access Time

16

25

ns

TEHQX

Chip Enable Output Enable Time

12

5

ns

TELQZ

Chip Enable Output Disable Time

6

10

ns

TGLQV

Output Enable Access Time

4

9

ns

TGLQX

Output Enable Output Enable Time

4

2

ns

TGHQZ

Output Enable Output Disable Time

4

9

ns

READ CYCLE AC TIMING CHARACTERISTICS (1)

(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and

output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading C

capacitive output loading C

(2) Typical operating conditions: VDD=5.0 V, TA=25

°C, pre-radiation.

(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55

°C to 125°C, post total dose at 25°C.

Worst Case (3)

HIGH

IMPEDANCE

NCS

NOE

DATA VALID

CE

ADDRESS

(NWE = high)

DATA OUT

Symbol

Parameter

Typical

-55 to 125

Units

(2)

Min

Max