MC74HCT541A

http://onsemi.com

3

Guaranteed Limit

Symbol

Parameter

–55 to 25

°C

≤85°C

≤125°C

Unit

tPLH,

tPHL

Maximum Propagation Delay, Input A to Output Y

(Figures 1 and 3)

23

28

32

ns

tPLZ,

tPHZ

Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4)

30

34

38

ns

tPZL,

tPZH

Maximum Propagation Delay, Output Enable to Output Y

(Figures 2 and 4)

30

34

38

ns

tTLH,

tTHL

Maximum Output Transition Time, Any Output

(Figures 1 and 3)

12

15

18

ns

Cin

Maximum Input Capacitance

10

10

10

pF

Cout

Maximum Three–State Output Capacitance (Output in High Impedance

State)

15

15

15

pF

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON

Semiconductor High–Speed CMOS Data Book (DL129/D).

Typical @ 25

°C, VCC = 5.0 V

CPD

Power Dissipation Capacitance (Per Buffer)*

55

pF

* Used to determine the no–load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the

ON Semiconductor High–Speed CMOS Data Book (DL129/D).

Figure 1.

CL*

*Includes all probe and jig capacitance

TEST

POINT

OE1 or OE2

1.3V

3.0V

GND

OUTPUT Y

tPZL

OUTPUT Y

tPZH

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

10%

90%

tPLZ

tPHZ

1.3V

1.3V

Figure 2.

SWITCHING WAVEFORMS

DEVICE

UNDER

TEST

OUTPUT

TEST CIRCUITS

Figure 3.

Figure 4.

CL*

*Includes all probe and jig capacitance

TEST

POINT

DEVICE

UNDER

TEST

OUTPUT

1k

Ω

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ and tPZH.

3.0V

GND

INPUT A

OUTPUT Y

tPLH

tPHL

90%

1.3V

10%

tr

tTLH

tf

tTHL

90%

1.3V

10%

1.3V