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IDT71V65802S-100BQ Datasheet(PDF) 1 Page - Integrated Device Technology |
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IDT71V65802S-100BQ Datasheet(HTML) 1 Page - Integrated Device Technology |
1 / 26 page OCTOBER 2004 DSC-5303/05 1 ©2004 Integrated Device Technology, Inc. Pin Description Summary Description The IDT71V65602/5802 are 3.3V high-speed 9,437,184-bit (9 Megabit) synchronous SRAMs. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given the name ZBTTM, or Zero Bus Turnaround. Features x x x x x 256K x 36, 512K x 18 memory configurations x x x x x Supports high performance system speed - 150MHz (3.8ns Clock-to-Data Access) x x x x x ZBTTM Feature - No dead cycles between write and read cycles x x x x x Internally synchronized output buffer enable eliminates the need to control OE OE OE OE OE x x x x x Single R/ W W W W W (READ/WRITE) control pin x x x x x Positive clock-edge triggered address, data, and control signal registers for fully pipelined applications x x x x x 4-word burst capability (interleaved or linear) x x x x x Individual byte write ( BW BW BW BW BW1 - BW BW BW BW BW4) control (May tie active) x x x x x Three chip enables for simple depth expansion x x x x x 3.3V power supply (±5%) x x x x x 2.5V I/O Supply (VDDQ) x x x x x Power down controlled by ZZ input x x x x x Packaged in a JEDEC standard 100-pin plastic thin quad and flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball grid array (fBGA) A0-A18 Address Inputs Input Synchronous CE1, CE2, CE2 Chip Enables Input Synchronous OE Output Enable Input Asynchronous R/ W Read/Write Signal Input Synchronous CEN Clock Enable Input Synchronous BW1, BW2, BW3, BW4 Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV/ LD Advance burst address / Load new address Input Synchronous LBO Linear / Interleaved Burst Order Input Static ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, VDDQ Core Power, I/O Power Supply Static VSS Ground Supply Static 5303 tbl 01 256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs 2.5V I/O, Burst Counter Pipelined Outputs IDT71V65602 IDT71V65802 Address and control signals are applied to the SRAM during one clock cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite. The IDT71V65602/5802 contain data I/O, address and control signal registers.Outputenableistheonlyasynchronoussignalandcanbeusedto disabletheoutputsatanygiventime. A Clock Enable ( CEN) pin allows operation of the IDT71V65602/5802 tobesuspendedaslongasnecessary.Allsynchronousinputsareignored when ( CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious values. There are three chip enable pins ( CE1, CE2, CE2) that allow the user to deselect the device when desired. If any one of these three are not asserted when ADV/ LD is low, no new memory operation can be initiated. However,anypendingdatatransfers(readsorwrites)willbecompleted.The databuswilltri-statetwocyclesafterchipisdeselectedorawriteisinitiated. The IDT71V65602/5802 have an on-chip burst counter. In the burst mode, the IDT71V65602/5802 can provide four cycles of data for a single addresspresentedtotheSRAM.Theorderoftheburstsequenceisdefined bythe LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst sequence.TheADV/ LDsignalisusedtoloadanewexternaladdress(ADV/ LD= LOW) or increment the internal burst counter (ADV/LD= HIGH). The IDT71V65602/5802 SRAM utilize IDT's latest high-performance CMOSprocess,andarepackagedinaJEDECStandard14mmx20mm100- pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and a 165 fine pitch ball grid array (fBGA). ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc. |
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