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IDT71V65802S-100BQ Datasheet(PDF) 10 Page - Integrated Device Technology |
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IDT71V65802S-100BQ Datasheet(HTML) 10 Page - Integrated Device Technology |
10 / 26 page 6.42 10 IDT71V65602, IDT71V65802, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with ZBT ™ ™ ™ ™ ™ Feature, 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges Linear Burst Sequence Table (LBO=VSS) Interleaved Burst Sequence Table (LBO=VDD) Functional Timing Diagram(1) NOTES: 1. This assumes CEN, CE1, CE2, CE2 are all true. 2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay from the rising edge of clock. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting. Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 111 00 1 0 0 5303 tbl 10 Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 11 000 11 0 5303 tbl 11 n+29 A29 C29 D/Q27 ADDRESS (2) (A0 - A17) CONTROL (2) (R/ W,ADV/LD, BWx) DATA (2) I/O [0:31], I/O P[1:4] CYCLE CLOCK n+30 A30 C30 D/Q28 n+31 A31 C31 D/Q29 n+32 A32 C32 D/Q30 n+33 A33 C33 D/Q31 n+34 A34 C34 D/Q32 n+35 A35 C35 D/Q33 n+36 A36 C36 D/Q34 n+37 A37 C37 D/Q35 5303 drw 03 , |
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