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M5M5V416BWG-85HI Datasheet(PDF) 2 Page - Mitsubishi Electric Semiconductor |
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M5M5V416BWG-85HI Datasheet(HTML) 2 Page - Mitsubishi Electric Semiconductor |
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2 / 10 page  M ITSUBISHI ELECTRIC M5M5V416BWG revision-W03, ' 98.12.16 4194304-BIT (262144-WORD BY 16-BIT) CMOS STATIC RAM MITSUBISHI LSIs PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change 2 FUNCTION The M5M5V416BWG is organized as 262,144-words by 16-bit. These dev ices operate on a single +2.7~3.6V power supply, and are directly TTL compatible to both input and output. Its f ully st atic circuit needs no clocks and no ref resh, and makes it usef ul. The operation mode are determined by a combination of the dev ice control inputs BC1 , BC2 , S1, S2 , W and OE. Each mode is summarized in the f unction table. A write operation is executed whenev er the low lev el W ov erlaps with the low lev el BC1 and/or BC2 and the low lev el S1 and the high lev el S2. The address(A0~A17) must be set up bef ore the write cy cle and must be stable during the entire cycle. A read operation is executed by s etting W at a high lev el and OE at a low lev el while BC1 and/or BC2 and S1 and S2 are in an activ e state(S1=L,S2=H). When setting BC1 at the high lev el and other pins are in an activ e stage , upper-byt e are in a selectable mode in which both reading and writing are enabled, and lower-byte are in a non-selectable mode. And when setting BC2 at a high lev el and other pins are in an activ e stage, lower- byt e are in a selectable mode and upper-by te are in a non-selectable mode. When setting BC1 and BC2 at a high lev el or S1 at a high lev el or S2 at a low lev el, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR-tie with other chips and memory expansion by BC1, BC2 and S1, S2. The power supply c urrent is reduced as low as 0.3µA(25°C, ty pical), and the memory data can be held at +2V power supply, enabling battery back-up operation during power f ailure or power-down operation in the non-selected mode. BLOCK DIAGRAM MEMORY ARRAY 262144 WORDS x 16 BITS CLOCK GENERATOR A0 A1 A16 A17 S2 BC1 BC2 W OE DQ 8 DQ 1 DQ 16 DQ 9 - Vcc GND S1 FUNCTION TABLE Mode S2 W H X X High-Z BC1 BC2 OE DQ1~8 X X Non selection DQ9~16 Icc High-Z Standby High-Z High-Z H X L L H Din High-Z Active H H L H Read High-Z Dout Active L H H L Active H H L Active H L High-Z High-Z Active H L H H High-Z H L Dout H L L Read Dout Active H L Din L L X Write Din Active H High-Z H H High-Z High-Z Non selection X H H X X Standby Write H H L L Write Din Active X H L H Read High-Z Active L Dout H High-Z S1 H L L L L L L L X L L L X X High-Z X X Non selection High-Z Standby L L X X High-Z X X Non selection High-Z Standby H |
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Similar Description - M5M5V416BWG-85HI |
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