CY7C1316AV18
CY7C1318AV18
CY7C1320AV18
Document #: 38-05499 Rev. *B
Page 5 of 20
R/W
Input-
Synchronous
Synchronous Read/Write Input. When LD is LOW, this input designates the access type (Read
when R/W is HIGH, Write when R/W is LOW) for loaded address. R/W must meet the set-up and
hold times around edge of K.
C
Input-
Clock
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
C
Input-
Clock
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from
the device. C and C can be used together to deskew the flight times of various devices on the
board back to the controller. See application example for further details.
K
Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the
device and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated
on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous data being presented to the device
and to drive out data through Q[x:0] when in single clock mode.
CQ
Output-
Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
CQ
Output-
Clock
CQ is referenced with respect to C. This is a free-running clock and is synchronized to the
output clock (C) of the DDR-II. In the single clock mode, CQ is generated with respect to K. The
timings for the echo clocks are shown in the AC timing table.
ZQ
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system
data bus impedance. CQ, CQ, and Q[x:0] output impedance are set to 0.2 × RQ, where RQ is a
resistor connected between ZQ and ground. Alternately, this pin can be connected directly to VDD,
which enables the minimum impedance mode. This pin cannot be connected directly to GND or
left unconnected.
DOFF
Input
DLL Turn Off—active LOW. Connecting this pin to ground will turn off the DLL inside the device.
The timings in the DLL turned off operation will be different from those listed in this data sheet.
More details on this operation can be found in the application note, “DLL Operation in the
QDR™-II.”
TDO
Output
TDO for JTAG.
TCK
Input
TCK pin for JTAG.
TDI
Input
TDI pin for JTAG.
TMS
Input
TMS pin for JTAG.
NC
N/A
Not connected to the die. Can be tied to any voltage level.
NC/36M
N/A
Address expansion for 36M. This is not connected to the die and so can be tied to any voltage
level.
NC/72M
N/A
Address expansion for 72M. This is not connected to the die and so can be tied to any voltage
level.
VSS/72M
Input
Address expansion for 72M. This must be tied LOW.
VSS/144M
Input
Address expansion for 144M. This must be tied LOW.
VSS/288M
Input
Address expansion for 288M. This must be tied LOW.
VREF
Input-
Reference
Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs
as well as AC measurement points.
VDD
Power Supply Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power Supply Power supply inputs for the outputs of the device.
Pin Definitions (continued)
Pin Name
I/O
Pin Description
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