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M5M5Y5672TG-20 Datasheet(PDF) 1 Page - Mitsubishi Electric Semiconductor |
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M5M5Y5672TG-20 Datasheet(HTML) 1 Page - Mitsubishi Electric Semiconductor |
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1 / 27 page  MITSUBISHI LSIs M5M5Y5672TG – 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM 1 MITSUBISHI ELECTRIC Advanced Information M5M5Y5672TG REV.0.1 DESCRIPTION The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, providing greater reliability. M5M5Y5672TG operates on a single 1.8V power supply and are 1.8V CMOS compatible. FEATURES • Fully registered inputs and outputs for pipelined operation • Fast clock speed: 250, 225, and 200 MHz • Fast access time: 2.6, 2.8, 3.2 ns • Single 1.8V +150/-100mV power supply VDD • Separate VDDQ for 1.8V I/O • Individual byte write (BWa# - BWh#) controls may be tied LOW • Single Read/Write control pin (W#) • Echo Clock outputs track data output drivers • ZQ mode pin for user-selectable output drive strength • 2 User programmable chip enable inputs for easy depth expansion • Linear or Interleaved Burst Modes • JTAG boundary scan support APPLICATION High-end networking products that require high bandwidth, such as switches and routers. FUNCTION Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition. Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BWf#, BWg#, BWh#), Echo Clock outputs (CQ1, CQ1#, CQ2, CQ2#) and Read/Write (W#). Write operations are controlled by the eight Byte Write Enables (BWa# - BWh#) and Read/Write(W#) inputs. All writes are conducted with on-chip synchronous self-timed write circuitry. The Echo Clocks are delayed copies of the RAM clock, CLK. Echo Clocks are designed to track changes in output driver delays due to variance in die temperature and supply voltage. The ZQ pin supplied with selectable impedance drivers, allows selection between nominal drive strength (ZQ LOW) for multi-drop bus application and low drive strength (ZQ floating or HIGH) point-to-point applications. The sense of two User-Programmable Chip Enable inputs (E2, E3), whether they function as active LOW or active HIGH inputs, is determined by the state of the programming inputs, EP2 and EP3. The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved burst, or a linear burst. All read, write and deselect cycles are initiated by the ADV Low input. Subsequent burst address can be internally generated as controlled by the ADV HIGH input. PACKAGE PART NAME TABLE Bump Body Size Bump Pitch M5M5Y5672TG 209(11X19) bump BGA 14mm X 22mm 1mm Part Name Frequency Access Cycle Active Current (max.) Standby Current (max.) M5M5Y5672TG -25 250MHz 2.6ns 4.0ns 550mA 20mA M5M5Y5672TG -22 225MHz 2.8ns 4.4ns 500mA 20mA M5M5Y5672TG -20 200MHz 3.2ns 5.0ns 450mA 20mA 2001.May Rev.0.1 Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. |
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